//------------------------------------------------
// top.v
// David_Harris@hmc.edu 9 November 2005
// npinckney@hmc.edu 12 February 2007
// Carl Nygaard carlpny at gmail dot com 2007
//
// Top level system including MIPS and memories
//------------------------------------------------

`timescale 1 ns / 1 ps

module top(input         ph1, ph2, reset,
           input  [7:0]        interrupts,
           output [31:0] writedata, dataadr, 
           output        memwrite);


  wire [31:0] memadr;
  wire [31:0] memdata;
  wire [3:0] membyteen;
  wire memrwb;
  wire memen;
  wire memdone;
  
  // These are hooks for testing
  assign memwrite = ~memrwb & memen;
  assign writedata = memdata;
  assign dataadr = memadr;
   
  // instantiate processor and memories
  chip thechip(ph1, ph2, reset, interrupts, memadr, memdata, membyteen, memrwb, memen, memdone);
  extmem extmem(ph1, ph2, reset, memadr[14:2], memdata, membyteen, memrwb, memen, memdone);

endmodule









/* Verilog for cell 'chip{sch}' from library 'MIPS' */
/* Created on Fri Apr 20, 2007 04:25:41 */
/* Last revised on Wed Apr 25, 2007 15:52:42 */
/* Written on Wed Apr 25, 2007 16:44:00 by Electric VLSI Design System, version 8.04 */

module muddlib07__and2_4x(a, b, y);
  input a;
  input b;
  output y;

  supply1 vdd;
  supply0 gnd;
  wire net_1, net_2;

  tranif1 nmos_0(net_1, net_2, b);
  tranif1 nmos_1(gnd, net_1, a);
  tranif1 nmos_2(gnd, y, net_2);
  tranif0 pmos_0(net_2, vdd, b);
  tranif0 pmos_1(net_2, vdd, a);
  tranif0 pmos_2(y, vdd, net_2);
endmodule   /* muddlib07__and2_4x */

module muddlib07__buf_8x(a, y);
  input a;
  output y;

  supply1 vdd;
  supply0 gnd;
  wire net_85;

  tranif1 nmos_1(gnd, y, net_85);
  tranif1 nmos_2(gnd, net_85, a);
  tranif1 nmos_3(gnd, y, net_85);
  tranif0 pmos_1(y, vdd, net_85);
  tranif0 pmos_2(net_85, vdd, a);
  tranif0 pmos_3(y, vdd, net_85);
endmodule   /* muddlib07__buf_8x */

module muddlib07__inv_1x(a, y);
  input a;
  output y;

  supply1 vdd;
  supply0 gnd;
  tranif1 nmos_0(gnd, y, a);
  tranif0 pmos_0(y, vdd, a);
endmodule   /* muddlib07__inv_1x */

module memsys_final__inv_16x(a, y);
  input a;
  output y;

  supply1 vdd;
  supply0 gnd;
  tranif1 nmos_0(gnd, y, a);
  tranif0 pmos_0(y, vdd, a);
endmodule   /* memsys_final__inv_16x */

module memsys_final__inv_64x(a, y);
  input a;
  output y;

  supply1 vdd;
  supply0 gnd;
  tranif1 nmos_0(gnd, y, a);
  tranif0 pmos_0(y, vdd, a);
endmodule   /* memsys_final__inv_64x */

module muddlib07__and2_1x(a, b, y);
  input a;
  input b;
  output y;

  supply1 vdd;
  supply0 gnd;
  wire net_1, net_2;

  tranif1 nmos_0(net_1, net_2, b);
  tranif1 nmos_1(gnd, net_1, a);
  tranif1 nmos_2(gnd, y, net_2);
  tranif0 pmos_0(net_2, vdd, b);
  tranif0 pmos_1(net_2, vdd, a);
  tranif0 pmos_2(y, vdd, net_2);
endmodule   /* muddlib07__and2_1x */

module muddlib07__mux2_c_1x(d0, d1, s, y);
  input d0;
  input d1;
  input s;
  output y;

  supply1 vdd;
  supply0 gnd;
  wire net_12, net_15, net_3, net_4, net_5, sb;

  tranif1 nmos_0(gnd, net_3, d1);
  tranif1 nmos_1(gnd, net_4, d0);
  tranif1 nmos_2(net_3, net_5, s);
  tranif1 nmos_3(net_4, net_5, sb);
  tranif1 nmos_4(gnd, y, net_5);
  tranif1 nmos_5(gnd, sb, s);
  tranif0 pmos_0(net_5, net_15, sb);
  tranif0 pmos_1(net_15, vdd, d1);
  tranif0 pmos_2(net_5, net_12, s);
  tranif0 pmos_3(net_12, vdd, d0);
  tranif0 pmos_4(y, vdd, net_5);
  tranif0 pmos_5(sb, vdd, s);
endmodule   /* muddlib07__mux2_c_1x */

module muddlib07__buftri_dp_1x(d, en, enb, y);
  input d;
  input en;
  input enb;
  output y;

  supply1 vdd;
  supply0 gnd;
  wire net_1, net_3, net_6;

  tranif1 nmos_0(gnd, net_3, net_6);
  tranif1 nmos_1(net_3, y, en);
  tranif1 nmos_2(gnd, net_6, d);
  tranif0 pmos_0(y, net_1, enb);
  tranif0 pmos_1(net_1, vdd, net_6);
  tranif0 pmos_2(net_6, vdd, d);
endmodule   /* muddlib07__buftri_dp_1x */

module muddlib07__inv_4x(a, y);
  input a;
  output y;

  supply1 vdd;
  supply0 gnd;
  tranif1 nmos_0(gnd, y, a);
  tranif0 pmos_0(y, vdd, a);
endmodule   /* muddlib07__inv_4x */

module memsys_final__buftri_zip(en, en_out, enb_out);
  input en;
  output en_out;
  output enb_out;

  supply1 vdd;
  supply0 gnd;
  muddlib07__inv_4x inv_4x_0(.a(en), .y(enb_out));
  muddlib07__inv_4x inv_4x_1(.a(enb_out), .y(en_out));
endmodule   /* memsys_final__buftri_zip */

module memsys_final__buftri_1x_4(d, en, y);
  input [3:0] d;
  input en;
  output [3:0] y;

  supply1 vdd;
  supply0 gnd;
  wire net_17, net_18;

  muddlib07__buftri_dp_1x buftri_3_(.d(d[3]), .en(net_17), .enb(net_18), 
      .y(y[3]));
  muddlib07__buftri_dp_1x buftri_2_(.d(d[2]), .en(net_17), .enb(net_18), 
      .y(y[2]));
  muddlib07__buftri_dp_1x buftri_1_(.d(d[1]), .en(net_17), .enb(net_18), 
      .y(y[1]));
  muddlib07__buftri_dp_1x buftri_0_(.d(d[0]), .en(net_17), .enb(net_18), 
      .y(y[0]));
  memsys_final__buftri_zip buftri_z_0(.en(en), .en_out(net_17), 
      .enb_out(net_18));
endmodule   /* memsys_final__buftri_1x_4 */

module muddlib07__buftri_c_1x(d, en, y);
  input d;
  input en;
  output y;

  supply1 vdd;
  supply0 gnd;
  wire net_1, net_3, net_54, net_6;

  tranif1 nmos_0(gnd, net_3, net_6);
  tranif1 nmos_1(net_3, y, en);
  tranif1 nmos_2(gnd, net_54, en);
  tranif1 nmos_3(gnd, net_6, d);
  tranif0 pmos_0(y, net_1, net_54);
  tranif0 pmos_1(net_1, vdd, net_6);
  tranif0 pmos_2(net_54, vdd, en);
  tranif0 pmos_3(net_6, vdd, d);
endmodule   /* muddlib07__buftri_c_1x */

module memsys_final__blueblock(dmembyteen, dmemen, don, memdone, swcb_dmemrwbb, 
      wbdone, dmemdone, wbbyteen, wben);
  input [3:0] dmembyteen;
  input dmemen;
  input don;
  input memdone;
  input swcb_dmemrwbb;
  input wbdone;
  output dmemdone;
  output [3:0] wbbyteen;
  output wben;

  supply1 vdd;
  supply0 gnd;
  wire dmemdonemem;

  muddlib07__mux2_c_1x dmemdonememmux(.d0(gnd), .d1(memdone), .s(don), 
      .y(dmemdonemem));
  muddlib07__mux2_c_1x dmemdonemux(.d0(dmemdonemem), .d1(wbdone), 
      .s(swcb_dmemrwbb), .y(dmemdone));
  memsys_final__buftri_1x_4 wbbyteend(.d(dmembyteen[3:0]), .en(swcb_dmemrwbb), 
      .y(wbbyteen[3:0]));
  muddlib07__buftri_c_1x wbend(.d(dmemen), .en(swcb_dmemrwbb), .y(wben));
endmodule   /* memsys_final__blueblock */

module memsys_final__cmux2_dp_1x(d0, d1, s, sb, y0, y1);
  input d0;
  input d1;
  input s;
  input sb;
  output y0;
  output y1;

  supply1 vdd;
  supply0 gnd;
  wire net_0, net_1, net_10, net_11, net_12, net_13, net_4, net_5, net_6, net_9;

  tranif1 nmos_0(net_0, net_4, sb);
  tranif1 nmos_1(gnd, net_0, d1);
  tranif1 nmos_2(net_1, net_4, s);
  tranif1 nmos_3(gnd, net_1, d0);
  tranif1 nmos_4(net_5, net_9, s);
  tranif1 nmos_5(gnd, net_5, d1);
  tranif1 nmos_6(net_6, net_9, sb);
  tranif1 nmos_7(gnd, net_6, d0);
  tranif1 nmos_8(gnd, y1, net_4);
  tranif1 nmos_9(gnd, y0, net_9);
  tranif0 pmos_0(net_4, net_12, sb);
  tranif0 pmos_1(net_12, vdd, d0);
  tranif0 pmos_2(net_4, net_13, s);
  tranif0 pmos_3(net_13, vdd, d1);
  tranif0 pmos_4(net_9, net_11, sb);
  tranif0 pmos_5(net_11, vdd, d1);
  tranif0 pmos_6(net_10, vdd, d0);
  tranif0 pmos_7(net_9, net_10, s);
  tranif0 pmos_8(y1, vdd, net_4);
  tranif0 pmos_9(y0, vdd, net_9);
endmodule   /* memsys_final__cmux2_dp_1x */

module memsys_final__cmux2_zip(s, s_out, sb_out);
  input s;
  output s_out;
  output sb_out;

  supply1 vdd;
  supply0 gnd;
  muddlib07__inv_4x inv_4x_0(.a(s), .y(sb_out));
  muddlib07__inv_4x inv_4x_1(.a(sb_out), .y(s_out));
endmodule   /* memsys_final__cmux2_zip */

module memsys_final__cmux2_1x_32(d0, d1, s, y0, y1);
  input [31:0] d0;
  input [31:0] d1;
  input s;
  output [31:0] y0;
  output [31:0] y1;

  supply1 vdd;
  supply0 gnd;
  wire sb, sbb;

  memsys_final__cmux2_dp_1x cmux2_31_(.d0(d0[31]), .d1(d1[31]), .s(sbb), 
      .sb(sb), .y0(y0[31]), .y1(y1[31]));
  memsys_final__cmux2_dp_1x cmux2_30_(.d0(d0[30]), .d1(d1[30]), .s(sbb), 
      .sb(sb), .y0(y0[30]), .y1(y1[30]));
  memsys_final__cmux2_dp_1x cmux2_29_(.d0(d0[29]), .d1(d1[29]), .s(sbb), 
      .sb(sb), .y0(y0[29]), .y1(y1[29]));
  memsys_final__cmux2_dp_1x cmux2_28_(.d0(d0[28]), .d1(d1[28]), .s(sbb), 
      .sb(sb), .y0(y0[28]), .y1(y1[28]));
  memsys_final__cmux2_dp_1x cmux2_27_(.d0(d0[27]), .d1(d1[27]), .s(sbb), 
      .sb(sb), .y0(y0[27]), .y1(y1[27]));
  memsys_final__cmux2_dp_1x cmux2_26_(.d0(d0[26]), .d1(d1[26]), .s(sbb), 
      .sb(sb), .y0(y0[26]), .y1(y1[26]));
  memsys_final__cmux2_dp_1x cmux2_25_(.d0(d0[25]), .d1(d1[25]), .s(sbb), 
      .sb(sb), .y0(y0[25]), .y1(y1[25]));
  memsys_final__cmux2_dp_1x cmux2_24_(.d0(d0[24]), .d1(d1[24]), .s(sbb), 
      .sb(sb), .y0(y0[24]), .y1(y1[24]));
  memsys_final__cmux2_dp_1x cmux2_23_(.d0(d0[23]), .d1(d1[23]), .s(sbb), 
      .sb(sb), .y0(y0[23]), .y1(y1[23]));
  memsys_final__cmux2_dp_1x cmux2_22_(.d0(d0[22]), .d1(d1[22]), .s(sbb), 
      .sb(sb), .y0(y0[22]), .y1(y1[22]));
  memsys_final__cmux2_dp_1x cmux2_21_(.d0(d0[21]), .d1(d1[21]), .s(sbb), 
      .sb(sb), .y0(y0[21]), .y1(y1[21]));
  memsys_final__cmux2_dp_1x cmux2_20_(.d0(d0[20]), .d1(d1[20]), .s(sbb), 
      .sb(sb), .y0(y0[20]), .y1(y1[20]));
  memsys_final__cmux2_dp_1x cmux2_19_(.d0(d0[19]), .d1(d1[19]), .s(sbb), 
      .sb(sb), .y0(y0[19]), .y1(y1[19]));
  memsys_final__cmux2_dp_1x cmux2_18_(.d0(d0[18]), .d1(d1[18]), .s(sbb), 
      .sb(sb), .y0(y0[18]), .y1(y1[18]));
  memsys_final__cmux2_dp_1x cmux2_17_(.d0(d0[17]), .d1(d1[17]), .s(sbb), 
      .sb(sb), .y0(y0[17]), .y1(y1[17]));
  memsys_final__cmux2_dp_1x cmux2_16_(.d0(d0[16]), .d1(d1[16]), .s(sbb), 
      .sb(sb), .y0(y0[16]), .y1(y1[16]));
  memsys_final__cmux2_dp_1x cmux2_15_(.d0(d0[15]), .d1(d1[15]), .s(sbb), 
      .sb(sb), .y0(y0[15]), .y1(y1[15]));
  memsys_final__cmux2_dp_1x cmux2_14_(.d0(d0[14]), .d1(d1[14]), .s(sbb), 
      .sb(sb), .y0(y0[14]), .y1(y1[14]));
  memsys_final__cmux2_dp_1x cmux2_13_(.d0(d0[13]), .d1(d1[13]), .s(sbb), 
      .sb(sb), .y0(y0[13]), .y1(y1[13]));
  memsys_final__cmux2_dp_1x cmux2_12_(.d0(d0[12]), .d1(d1[12]), .s(sbb), 
      .sb(sb), .y0(y0[12]), .y1(y1[12]));
  memsys_final__cmux2_dp_1x cmux2_11_(.d0(d0[11]), .d1(d1[11]), .s(sbb), 
      .sb(sb), .y0(y0[11]), .y1(y1[11]));
  memsys_final__cmux2_dp_1x cmux2_10_(.d0(d0[10]), .d1(d1[10]), .s(sbb), 
      .sb(sb), .y0(y0[10]), .y1(y1[10]));
  memsys_final__cmux2_dp_1x cmux2_9_(.d0(d0[9]), .d1(d1[9]), .s(sbb), .sb(sb), 
      .y0(y0[9]), .y1(y1[9]));
  memsys_final__cmux2_dp_1x cmux2_8_(.d0(d0[8]), .d1(d1[8]), .s(sbb), .sb(sb), 
      .y0(y0[8]), .y1(y1[8]));
  memsys_final__cmux2_dp_1x cmux2_7_(.d0(d0[7]), .d1(d1[7]), .s(sbb), .sb(sb), 
      .y0(y0[7]), .y1(y1[7]));
  memsys_final__cmux2_dp_1x cmux2_6_(.d0(d0[6]), .d1(d1[6]), .s(sbb), .sb(sb), 
      .y0(y0[6]), .y1(y1[6]));
  memsys_final__cmux2_dp_1x cmux2_5_(.d0(d0[5]), .d1(d1[5]), .s(sbb), .sb(sb), 
      .y0(y0[5]), .y1(y1[5]));
  memsys_final__cmux2_dp_1x cmux2_4_(.d0(d0[4]), .d1(d1[4]), .s(sbb), .sb(sb), 
      .y0(y0[4]), .y1(y1[4]));
  memsys_final__cmux2_dp_1x cmux2_3_(.d0(d0[3]), .d1(d1[3]), .s(sbb), .sb(sb), 
      .y0(y0[3]), .y1(y1[3]));
  memsys_final__cmux2_dp_1x cmux2_2_(.d0(d0[2]), .d1(d1[2]), .s(sbb), .sb(sb), 
      .y0(y0[2]), .y1(y1[2]));
  memsys_final__cmux2_dp_1x cmux2_1_(.d0(d0[1]), .d1(d1[1]), .s(sbb), .sb(sb), 
      .y0(y0[1]), .y1(y1[1]));
  memsys_final__cmux2_dp_1x cmux2_0_(.d0(d0[0]), .d1(d1[0]), .s(sbb), .sb(sb), 
      .y0(y0[0]), .y1(y1[0]));
  memsys_final__cmux2_zip cmux2_zi_0(.s(s), .s_out(sbb), .sb_out(sb));
endmodule   /* memsys_final__cmux2_1x_32 */

module memsys_final__cmux2_1x_4(d0, d1, s, y0, y1);
  input [3:0] d0;
  input [3:0] d1;
  input s;
  output [3:0] y0;
  output [3:0] y1;

  supply1 vdd;
  supply0 gnd;
  wire sb, sbb;

  memsys_final__cmux2_dp_1x cmux2_3_(.d0(d0[3]), .d1(d1[3]), .s(sbb), .sb(sb), 
      .y0(y0[3]), .y1(y1[3]));
  memsys_final__cmux2_dp_1x cmux2_2_(.d0(d0[2]), .d1(d1[2]), .s(sbb), .sb(sb), 
      .y0(y0[2]), .y1(y1[2]));
  memsys_final__cmux2_dp_1x cmux2_1_(.d0(d0[1]), .d1(d1[1]), .s(sbb), .sb(sb), 
      .y0(y0[1]), .y1(y1[1]));
  memsys_final__cmux2_dp_1x cmux2_0_(.d0(d0[0]), .d1(d1[0]), .s(sbb), .sb(sb), 
      .y0(y0[0]), .y1(y1[0]));
  memsys_final__cmux2_zip cmux2_zi_0(.s(s), .s_out(sbb), .sb_out(sb));
endmodule   /* memsys_final__cmux2_1x_4 */

module memsys_final__buftri_1x_32(d, en, y);
  input [31:0] d;
  input en;
  output [31:0] y;

  supply1 vdd;
  supply0 gnd;
  wire enb, enbb;

  muddlib07__buftri_dp_1x buftri_31_(.d(d[31]), .en(enbb), .enb(enb), 
      .y(y[31]));
  muddlib07__buftri_dp_1x buftri_30_(.d(d[30]), .en(enbb), .enb(enb), 
      .y(y[30]));
  muddlib07__buftri_dp_1x buftri_29_(.d(d[29]), .en(enbb), .enb(enb), 
      .y(y[29]));
  muddlib07__buftri_dp_1x buftri_28_(.d(d[28]), .en(enbb), .enb(enb), 
      .y(y[28]));
  muddlib07__buftri_dp_1x buftri_27_(.d(d[27]), .en(enbb), .enb(enb), 
      .y(y[27]));
  muddlib07__buftri_dp_1x buftri_26_(.d(d[26]), .en(enbb), .enb(enb), 
      .y(y[26]));
  muddlib07__buftri_dp_1x buftri_25_(.d(d[25]), .en(enbb), .enb(enb), 
      .y(y[25]));
  muddlib07__buftri_dp_1x buftri_24_(.d(d[24]), .en(enbb), .enb(enb), 
      .y(y[24]));
  muddlib07__buftri_dp_1x buftri_23_(.d(d[23]), .en(enbb), .enb(enb), 
      .y(y[23]));
  muddlib07__buftri_dp_1x buftri_22_(.d(d[22]), .en(enbb), .enb(enb), 
      .y(y[22]));
  muddlib07__buftri_dp_1x buftri_21_(.d(d[21]), .en(enbb), .enb(enb), 
      .y(y[21]));
  muddlib07__buftri_dp_1x buftri_20_(.d(d[20]), .en(enbb), .enb(enb), 
      .y(y[20]));
  muddlib07__buftri_dp_1x buftri_19_(.d(d[19]), .en(enbb), .enb(enb), 
      .y(y[19]));
  muddlib07__buftri_dp_1x buftri_18_(.d(d[18]), .en(enbb), .enb(enb), 
      .y(y[18]));
  muddlib07__buftri_dp_1x buftri_17_(.d(d[17]), .en(enbb), .enb(enb), 
      .y(y[17]));
  muddlib07__buftri_dp_1x buftri_16_(.d(d[16]), .en(enbb), .enb(enb), 
      .y(y[16]));
  muddlib07__buftri_dp_1x buftri_15_(.d(d[15]), .en(enbb), .enb(enb), 
      .y(y[15]));
  muddlib07__buftri_dp_1x buftri_14_(.d(d[14]), .en(enbb), .enb(enb), 
      .y(y[14]));
  muddlib07__buftri_dp_1x buftri_13_(.d(d[13]), .en(enbb), .enb(enb), 
      .y(y[13]));
  muddlib07__buftri_dp_1x buftri_12_(.d(d[12]), .en(enbb), .enb(enb), 
      .y(y[12]));
  muddlib07__buftri_dp_1x buftri_11_(.d(d[11]), .en(enbb), .enb(enb), 
      .y(y[11]));
  muddlib07__buftri_dp_1x buftri_10_(.d(d[10]), .en(enbb), .enb(enb), 
      .y(y[10]));
  muddlib07__buftri_dp_1x buftri_9_(.d(d[9]), .en(enbb), .enb(enb), .y(y[9]));
  muddlib07__buftri_dp_1x buftri_8_(.d(d[8]), .en(enbb), .enb(enb), .y(y[8]));
  muddlib07__buftri_dp_1x buftri_7_(.d(d[7]), .en(enbb), .enb(enb), .y(y[7]));
  muddlib07__buftri_dp_1x buftri_6_(.d(d[6]), .en(enbb), .enb(enb), .y(y[6]));
  muddlib07__buftri_dp_1x buftri_5_(.d(d[5]), .en(enbb), .enb(enb), .y(y[5]));
  muddlib07__buftri_dp_1x buftri_4_(.d(d[4]), .en(enbb), .enb(enb), .y(y[4]));
  muddlib07__buftri_dp_1x buftri_3_(.d(d[3]), .en(enbb), .enb(enb), .y(y[3]));
  muddlib07__buftri_dp_1x buftri_2_(.d(d[2]), .en(enbb), .enb(enb), .y(y[2]));
  muddlib07__buftri_dp_1x buftri_1_(.d(d[1]), .en(enbb), .enb(enb), .y(y[1]));
  muddlib07__buftri_dp_1x buftri_0_(.d(d[0]), .en(enbb), .enb(enb), .y(y[0]));
  memsys_final__buftri_zip buftri_z_0(.en(en), .en_out(enbb), .enb_out(enb));
endmodule   /* memsys_final__buftri_1x_32 */

module muddlib07__mux4_dp_1x(d0, d1, d2, d3, s0, s0b, s1, s1b, y);
  input d0;
  input d1;
  input d2;
  input d3;
  input s0;
  input s0b;
  input s1;
  input s1b;
  output y;

  supply1 vdd;
  supply0 gnd;
  wire net_28, net_29, net_30, net_5, net_50, net_51, net_56, net_57, net_58;
  wire net_6, net_68, net_70, net_8;

  tranif1 nmos_0(gnd, net_5, d0);
  tranif1 nmos_1(gnd, net_6, d1);
  tranif1 nmos_3(net_5, net_8, s0b);
  tranif1 nmos_4(net_6, net_8, s0);
  tranif1 nmos_5(net_8, net_50, s1b);
  tranif1 nmos_7(gnd, net_70, d3);
  tranif1 nmos_8(net_68, net_51, s0b);
  tranif1 nmos_9(net_70, net_51, s0);
  tranif1 nmos_10(net_51, net_50, s1);
  tranif1 nmos_11(gnd, net_68, d2);
  tranif1 nmos_12(gnd, y, net_50);
  tranif0 pmos_0(net_50, net_30, s1);
  tranif0 pmos_2(net_30, net_28, s0);
  tranif0 pmos_3(net_28, vdd, d0);
  tranif0 pmos_4(net_30, net_29, s0b);
  tranif0 pmos_5(net_29, vdd, d1);
  tranif0 pmos_7(net_58, net_56, s0);
  tranif0 pmos_8(net_56, vdd, d2);
  tranif0 pmos_9(net_58, net_57, s0b);
  tranif0 pmos_10(net_57, vdd, d3);
  tranif0 pmos_11(net_50, net_58, s1b);
  tranif0 pmos_12(y, vdd, net_50);
endmodule   /* muddlib07__mux4_dp_1x */

module memsys_final__mux4_zip(s, s0_out, s0b_out, s1_out, s1b_out);
  input [1:0] s;
  output s0_out;
  output s0b_out;
  output s1_out;
  output s1b_out;

  supply1 vdd;
  supply0 gnd;
  muddlib07__inv_4x inv_4x_4(.a(s[1]), .y(s1b_out));
  muddlib07__inv_4x inv_4x_5(.a(s[0]), .y(s0b_out));
  muddlib07__inv_4x inv_4x_6(.a(s1b_out), .y(s1_out));
  muddlib07__inv_4x inv_4x_7(.a(s0b_out), .y(s0_out));
endmodule   /* memsys_final__mux4_zip */

module memsys_final__mux4_1x_27(d0, d1, d2, d3, s, y);
  input [26:0] d0;
  input [26:0] d1;
  input [26:0] d2;
  input [26:0] d3;
  input [1:0] s;
  output [26:0] y;

  supply1 vdd;
  supply0 gnd;
  wire s0b, s0bb, s1b, s1bb;

  muddlib07__mux4_dp_1x mux4_26_(.d0(d0[26]), .d1(d1[26]), .d2(d2[26]), 
      .d3(d3[26]), .s0(s0bb), .s0b(s0b), .s1(s1bb), .s1b(s1b), .y(y[26]));
  muddlib07__mux4_dp_1x mux4_25_(.d0(d0[25]), .d1(d1[25]), .d2(d2[25]), 
      .d3(d3[25]), .s0(s0bb), .s0b(s0b), .s1(s1bb), .s1b(s1b), .y(y[25]));
  muddlib07__mux4_dp_1x mux4_24_(.d0(d0[24]), .d1(d1[24]), .d2(d2[24]), 
      .d3(d3[24]), .s0(s0bb), .s0b(s0b), .s1(s1bb), .s1b(s1b), .y(y[24]));
  muddlib07__mux4_dp_1x mux4_23_(.d0(d0[23]), .d1(d1[23]), .d2(d2[23]), 
      .d3(d3[23]), .s0(s0bb), .s0b(s0b), .s1(s1bb), .s1b(s1b), .y(y[23]));
  muddlib07__mux4_dp_1x mux4_22_(.d0(d0[22]), .d1(d1[22]), .d2(d2[22]), 
      .d3(d3[22]), .s0(s0bb), .s0b(s0b), .s1(s1bb), .s1b(s1b), .y(y[22]));
  muddlib07__mux4_dp_1x mux4_21_(.d0(d0[21]), .d1(d1[21]), .d2(d2[21]), 
      .d3(d3[21]), .s0(s0bb), .s0b(s0b), .s1(s1bb), .s1b(s1b), .y(y[21]));
  muddlib07__mux4_dp_1x mux4_20_(.d0(d0[20]), .d1(d1[20]), .d2(d2[20]), 
      .d3(d3[20]), .s0(s0bb), .s0b(s0b), .s1(s1bb), .s1b(s1b), .y(y[20]));
  muddlib07__mux4_dp_1x mux4_19_(.d0(d0[19]), .d1(d1[19]), .d2(d2[19]), 
      .d3(d3[19]), .s0(s0bb), .s0b(s0b), .s1(s1bb), .s1b(s1b), .y(y[19]));
  muddlib07__mux4_dp_1x mux4_18_(.d0(d0[18]), .d1(d1[18]), .d2(d2[18]), 
      .d3(d3[18]), .s0(s0bb), .s0b(s0b), .s1(s1bb), .s1b(s1b), .y(y[18]));
  muddlib07__mux4_dp_1x mux4_17_(.d0(d0[17]), .d1(d1[17]), .d2(d2[17]), 
      .d3(d3[17]), .s0(s0bb), .s0b(s0b), .s1(s1bb), .s1b(s1b), .y(y[17]));
  muddlib07__mux4_dp_1x mux4_16_(.d0(d0[16]), .d1(d1[16]), .d2(d2[16]), 
      .d3(d3[16]), .s0(s0bb), .s0b(s0b), .s1(s1bb), .s1b(s1b), .y(y[16]));
  muddlib07__mux4_dp_1x mux4_15_(.d0(d0[15]), .d1(d1[15]), .d2(d2[15]), 
      .d3(d3[15]), .s0(s0bb), .s0b(s0b), .s1(s1bb), .s1b(s1b), .y(y[15]));
  muddlib07__mux4_dp_1x mux4_14_(.d0(d0[14]), .d1(d1[14]), .d2(d2[14]), 
      .d3(d3[14]), .s0(s0bb), .s0b(s0b), .s1(s1bb), .s1b(s1b), .y(y[14]));
  muddlib07__mux4_dp_1x mux4_13_(.d0(d0[13]), .d1(d1[13]), .d2(d2[13]), 
      .d3(d3[13]), .s0(s0bb), .s0b(s0b), .s1(s1bb), .s1b(s1b), .y(y[13]));
  muddlib07__mux4_dp_1x mux4_12_(.d0(d0[12]), .d1(d1[12]), .d2(d2[12]), 
      .d3(d3[12]), .s0(s0bb), .s0b(s0b), .s1(s1bb), .s1b(s1b), .y(y[12]));
  muddlib07__mux4_dp_1x mux4_11_(.d0(d0[11]), .d1(d1[11]), .d2(d2[11]), 
      .d3(d3[11]), .s0(s0bb), .s0b(s0b), .s1(s1bb), .s1b(s1b), .y(y[11]));
  muddlib07__mux4_dp_1x mux4_10_(.d0(d0[10]), .d1(d1[10]), .d2(d2[10]), 
      .d3(d3[10]), .s0(s0bb), .s0b(s0b), .s1(s1bb), .s1b(s1b), .y(y[10]));
  muddlib07__mux4_dp_1x mux4_9_(.d0(d0[9]), .d1(d1[9]), .d2(d2[9]), .d3(d3[9]), 
      .s0(s0bb), .s0b(s0b), .s1(s1bb), .s1b(s1b), .y(y[9]));
  muddlib07__mux4_dp_1x mux4_8_(.d0(d0[8]), .d1(d1[8]), .d2(d2[8]), .d3(d3[8]), 
      .s0(s0bb), .s0b(s0b), .s1(s1bb), .s1b(s1b), .y(y[8]));
  muddlib07__mux4_dp_1x mux4_7_(.d0(d0[7]), .d1(d1[7]), .d2(d2[7]), .d3(d3[7]), 
      .s0(s0bb), .s0b(s0b), .s1(s1bb), .s1b(s1b), .y(y[7]));
  muddlib07__mux4_dp_1x mux4_6_(.d0(d0[6]), .d1(d1[6]), .d2(d2[6]), .d3(d3[6]), 
      .s0(s0bb), .s0b(s0b), .s1(s1bb), .s1b(s1b), .y(y[6]));
  muddlib07__mux4_dp_1x mux4_5_(.d0(d0[5]), .d1(d1[5]), .d2(d2[5]), .d3(d3[5]), 
      .s0(s0bb), .s0b(s0b), .s1(s1bb), .s1b(s1b), .y(y[5]));
  muddlib07__mux4_dp_1x mux4_4_(.d0(d0[4]), .d1(d1[4]), .d2(d2[4]), .d3(d3[4]), 
      .s0(s0bb), .s0b(s0b), .s1(s1bb), .s1b(s1b), .y(y[4]));
  muddlib07__mux4_dp_1x mux4_3_(.d0(d0[3]), .d1(d1[3]), .d2(d2[3]), .d3(d3[3]), 
      .s0(s0bb), .s0b(s0b), .s1(s1bb), .s1b(s1b), .y(y[3]));
  muddlib07__mux4_dp_1x mux4_2_(.d0(d0[2]), .d1(d1[2]), .d2(d2[2]), .d3(d3[2]), 
      .s0(s0bb), .s0b(s0b), .s1(s1bb), .s1b(s1b), .y(y[2]));
  muddlib07__mux4_dp_1x mux4_1_(.d0(d0[1]), .d1(d1[1]), .d2(d2[1]), .d3(d3[1]), 
      .s0(s0bb), .s0b(s0b), .s1(s1bb), .s1b(s1b), .y(y[1]));
  muddlib07__mux4_dp_1x mux4_0_(.d0(d0[0]), .d1(d1[0]), .d2(d2[0]), .d3(d3[0]), 
      .s0(s0bb), .s0b(s0b), .s1(s1bb), .s1b(s1b), .y(y[0]));
  memsys_final__mux4_zip mux4_zip_1(.s(s[1:0]), .s0_out(s0bb), .s0b_out(s0b), 
      .s1_out(s1bb), .s1b_out(s1b));
endmodule   /* memsys_final__mux4_1x_27 */

module memsys_final__buftri_1x_27(d, en, y);
  input [26:0] d;
  input en;
  output [26:0] y;

  supply1 vdd;
  supply0 gnd;
  wire enb, enbb;

  muddlib07__buftri_dp_1x buftri_26_(.d(d[26]), .en(enbb), .enb(enb), 
      .y(y[26]));
  muddlib07__buftri_dp_1x buftri_25_(.d(d[25]), .en(enbb), .enb(enb), 
      .y(y[25]));
  muddlib07__buftri_dp_1x buftri_24_(.d(d[24]), .en(enbb), .enb(enb), 
      .y(y[24]));
  muddlib07__buftri_dp_1x buftri_23_(.d(d[23]), .en(enbb), .enb(enb), 
      .y(y[23]));
  muddlib07__buftri_dp_1x buftri_22_(.d(d[22]), .en(enbb), .enb(enb), 
      .y(y[22]));
  muddlib07__buftri_dp_1x buftri_21_(.d(d[21]), .en(enbb), .enb(enb), 
      .y(y[21]));
  muddlib07__buftri_dp_1x buftri_20_(.d(d[20]), .en(enbb), .enb(enb), 
      .y(y[20]));
  muddlib07__buftri_dp_1x buftri_19_(.d(d[19]), .en(enbb), .enb(enb), 
      .y(y[19]));
  muddlib07__buftri_dp_1x buftri_18_(.d(d[18]), .en(enbb), .enb(enb), 
      .y(y[18]));
  muddlib07__buftri_dp_1x buftri_17_(.d(d[17]), .en(enbb), .enb(enb), 
      .y(y[17]));
  muddlib07__buftri_dp_1x buftri_16_(.d(d[16]), .en(enbb), .enb(enb), 
      .y(y[16]));
  muddlib07__buftri_dp_1x buftri_15_(.d(d[15]), .en(enbb), .enb(enb), 
      .y(y[15]));
  muddlib07__buftri_dp_1x buftri_14_(.d(d[14]), .en(enbb), .enb(enb), 
      .y(y[14]));
  muddlib07__buftri_dp_1x buftri_13_(.d(d[13]), .en(enbb), .enb(enb), 
      .y(y[13]));
  muddlib07__buftri_dp_1x buftri_12_(.d(d[12]), .en(enbb), .enb(enb), 
      .y(y[12]));
  muddlib07__buftri_dp_1x buftri_11_(.d(d[11]), .en(enbb), .enb(enb), 
      .y(y[11]));
  muddlib07__buftri_dp_1x buftri_10_(.d(d[10]), .en(enbb), .enb(enb), 
      .y(y[10]));
  muddlib07__buftri_dp_1x buftri_9_(.d(d[9]), .en(enbb), .enb(enb), .y(y[9]));
  muddlib07__buftri_dp_1x buftri_8_(.d(d[8]), .en(enbb), .enb(enb), .y(y[8]));
  muddlib07__buftri_dp_1x buftri_7_(.d(d[7]), .en(enbb), .enb(enb), .y(y[7]));
  muddlib07__buftri_dp_1x buftri_6_(.d(d[6]), .en(enbb), .enb(enb), .y(y[6]));
  muddlib07__buftri_dp_1x buftri_5_(.d(d[5]), .en(enbb), .enb(enb), .y(y[5]));
  muddlib07__buftri_dp_1x buftri_4_(.d(d[4]), .en(enbb), .enb(enb), .y(y[4]));
  muddlib07__buftri_dp_1x buftri_3_(.d(d[3]), .en(enbb), .enb(enb), .y(y[3]));
  muddlib07__buftri_dp_1x buftri_2_(.d(d[2]), .en(enbb), .enb(enb), .y(y[2]));
  muddlib07__buftri_dp_1x buftri_1_(.d(d[1]), .en(enbb), .enb(enb), .y(y[1]));
  muddlib07__buftri_dp_1x buftri_0_(.d(d[0]), .en(enbb), .enb(enb), .y(y[0]));
  memsys_final__buftri_zip buftri_z_0(.en(en), .en_out(enbb), .enb_out(enb));
endmodule   /* memsys_final__buftri_1x_27 */

module memsys_final__datapath(adrM, byteenM, dmemrwb_don, enM, imemrwb_ion, 
      memwriteMb, pcF, reF, state, swc, swc_imemrwbb, swc_memwriteM, 
      swcb_dmemrwbb, swcb_memwriteM, wbmemadr, wbmemdata, wbon, writedataM, 
      dadr, dbyteen, ddata, den, drwb, iadr, ibyteen, idata, ien, imemdata, 
      instrF, irwb, memadr, readdataM, wbadr, wbdata, dmemdata, memdata);
  input [29:0] adrM;
  input [3:0] byteenM;
  input dmemrwb_don;
  input enM;
  input imemrwb_ion;
  input memwriteMb;
  input [31:2] pcF;
  input reF;
  input [1:0] state;
  input swc;
  input swc_imemrwbb;
  input swc_memwriteM;
  input swcb_dmemrwbb;
  input swcb_memwriteM;
  input [26:0] wbmemadr;
  input [31:0] wbmemdata;
  input wbon;
  input [31:0] writedataM;
  output [29:0] dadr;
  output [3:0] dbyteen;
  output [31:0] ddata;
  output den;
  output drwb;
  output [29:0] iadr;
  output [3:0] ibyteen;
  output [31:0] idata;
  output ien;
  output [31:0] imemdata;
  output [31:0] instrF;
  output irwb;
  output [26:0] memadr;
  output [31:0] readdataM;
  output [26:0] wbadr;
  output [31:0] wbdata;
  input [31:0] dmemdata;
  input [31:0] memdata;

  supply1 vdd;
  supply0 gnd;
  memsys_final__cmux2_1x_32 adrmux(.d0({enM, memwriteMb, adrM[29], adrM[28], 
      adrM[27], adrM[26], adrM[25], adrM[24], adrM[23], adrM[22], adrM[21], 
      adrM[20], adrM[19], adrM[18], adrM[17], adrM[16], adrM[15], adrM[14], 
      adrM[13], adrM[12], adrM[11], adrM[10], adrM[9], adrM[8], adrM[7], 
      adrM[6], adrM[5], adrM[4], adrM[3], adrM[2], adrM[1], adrM[0]}), 
      .d1({reF, vdd, pcF[31], pcF[30], pcF[29], pcF[28], pcF[27], pcF[26], 
      pcF[25], pcF[24], pcF[23], pcF[22], pcF[21], pcF[20], pcF[19], pcF[18], 
      pcF[17], pcF[16], pcF[15], pcF[14], pcF[13], pcF[12], pcF[11], pcF[10], 
      pcF[9], pcF[8], pcF[7], pcF[6], pcF[5], pcF[4], pcF[3], pcF[2]}), 
      .s(swc), .y0({den, drwb, dadr[29], dadr[28], dadr[27], dadr[26], 
      dadr[25], dadr[24], dadr[23], dadr[22], dadr[21], dadr[20], dadr[19], 
      dadr[18], dadr[17], dadr[16], dadr[15], dadr[14], dadr[13], dadr[12], 
      dadr[11], dadr[10], dadr[9], dadr[8], dadr[7], dadr[6], dadr[5], dadr[4], 
      dadr[3], dadr[2], dadr[1], dadr[0]}), .y1({ien, irwb, iadr[29], iadr[28], 
      iadr[27], iadr[26], iadr[25], iadr[24], iadr[23], iadr[22], iadr[21], 
      iadr[20], iadr[19], iadr[18], iadr[17], iadr[16], iadr[15], iadr[14], 
      iadr[13], iadr[12], iadr[11], iadr[10], iadr[9], iadr[8], iadr[7], 
      iadr[6], iadr[5], iadr[4], iadr[3], iadr[2], iadr[1], iadr[0]}));
  memsys_final__cmux2_1x_4 byteenmux(.d0(byteenM[3:0]), .d1({gnd, gnd, gnd, 
      vdd}), .s(swc), .y0(dbyteen[3:0]), .y1(ibyteen[3:0]));
  memsys_final__cmux2_1x_32 datamux(.d0(ddata[31:0]), .d1(idata[31:0]), 
      .s(swc), .y0(readdataM[31:0]), .y1(instrF[31:0]));
  memsys_final__buftri_1x_32 ddatatri(.d(writedataM[31:0]), 
      .en(swcb_memwriteM), .y(ddata[31:0]));
  memsys_final__buftri_1x_32 dmemdatatri(.d(memdata[31:0]), .en(dmemrwb_don), 
      .y(dmemdata[31:0]));
  memsys_final__buftri_1x_32 idatatri(.d(writedataM[31:0]), .en(swc_memwriteM), 
      .y(idata[31:0]));
  memsys_final__buftri_1x_32 imemdatatri(.d(memdata[31:0]), .en(imemrwb_ion), 
      .y(imemdata[31:0]));
  memsys_final__mux4_1x_27 memadrmux(.d0({gnd, gnd, gnd, gnd, gnd, gnd, gnd, 
      gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, 
      gnd, gnd, gnd, gnd, gnd, gnd}), .d1(wbmemadr[26:0]), .d2(dadr[26:0]), 
      .d3(iadr[26:0]), .s(state[1:0]), .y(memadr[26:0]));
  memsys_final__buftri_1x_32 memdatatri(.d(wbmemdata[31:0]), .en(wbon), 
      .y(memdata[31:0]));
  memsys_final__buftri_1x_27 wbadrd(.d(dadr[26:0]), .en(swcb_dmemrwbb), 
      .y(wbadr[26:0]));
  memsys_final__buftri_1x_27 wbadri(.d(iadr[26:0]), .en(swc_imemrwbb), 
      .y(wbadr[26:0]));
  memsys_final__buftri_1x_32 wbdatad(.d(dmemdata[31:0]), .en(swcb_dmemrwbb), 
      .y(wbdata[31:0]));
  memsys_final__buftri_1x_32 wbdatai(.d(imemdata[31:0]), .en(swc_imemrwbb), 
      .y(wbdata[31:0]));
endmodule   /* memsys_final__datapath */

module muddlib07__and4_1x(a, b, c, d, y);
  input a;
  input b;
  input c;
  input d;
  output y;

  supply1 vdd;
  supply0 gnd;
  wire net_1, net_45, net_46, net_9;

  tranif1 nmos_0(net_45, net_9, c);
  tranif1 nmos_1(net_9, net_1, d);
  tranif1 nmos_3(gnd, y, net_1);
  tranif1 nmos_4(net_46, net_45, b);
  tranif1 nmos_6(gnd, net_46, a);
  tranif0 pmos_0(net_1, vdd, d);
  tranif0 pmos_1(y, vdd, net_1);
  tranif0 pmos_2(net_1, vdd, c);
  tranif0 pmos_3(net_1, vdd, b);
  tranif0 pmos_4(net_1, vdd, a);
endmodule   /* muddlib07__and4_1x */

module muddlib07__or2_1x(a, b, y);
  input a;
  input b;
  output y;

  supply1 vdd;
  supply0 gnd;
  wire net_58, net_71;

  tranif1 nmos_8(gnd, net_58, b);
  tranif1 nmos_10(gnd, y, net_58);
  tranif1 nmos_11(gnd, net_58, a);
  tranif0 pmos_2(net_58, net_71, b);
  tranif0 pmos_3(net_71, vdd, a);
  tranif0 pmos_4(y, vdd, net_58);
endmodule   /* muddlib07__or2_1x */

module memsys_final__byteenlog(byteen, memdone, reading, validnew);
  input [3:0] byteen;
  input memdone;
  input reading;
  output validnew;

  supply1 vdd;
  supply0 gnd;
  wire net_1, net_2;

  muddlib07__and2_1x and2_1x_0(.a(net_2), .b(memdone), .y(validnew));
  muddlib07__and4_1x and4_1x_0(.a(byteen[0]), .b(byteen[1]), .c(byteen[2]), 
      .d(byteen[3]), .y(net_1));
  muddlib07__or2_1x or2_1x_0(.a(net_1), .b(reading), .y(net_2));
endmodule   /* memsys_final__byteenlog */

module muddlib07__and3_1x(a, b, c, y);
  input a;
  input b;
  input c;
  output y;

  supply1 vdd;
  supply0 gnd;
  wire net_1, net_45, net_9;

  tranif1 nmos_0(net_45, net_9, b);
  tranif1 nmos_1(net_9, net_1, c);
  tranif1 nmos_3(gnd, y, net_1);
  tranif1 nmos_4(gnd, net_45, a);
  tranif0 pmos_0(net_1, vdd, c);
  tranif0 pmos_1(y, vdd, net_1);
  tranif0 pmos_2(net_1, vdd, a);
  tranif0 pmos_3(net_1, vdd, b);
endmodule   /* muddlib07__and3_1x */

module muddlib07__xnor2_1x(a, b, y);
  input a;
  input b;
  output y;

  supply1 vdd;
  supply0 gnd;
  wire ab, bb, net_3, net_4, net_7, net_8;

  tranif1 nmos_0(gnd, net_3, a);
  tranif1 nmos_1(gnd, net_4, ab);
  tranif1 nmos_2(net_3, y, bb);
  tranif1 nmos_3(net_4, y, b);
  tranif1 nmos_4(gnd, bb, b);
  tranif1 nmos_5(gnd, ab, a);
  tranif0 pmos_0(y, net_7, b);
  tranif0 pmos_1(net_7, vdd, a);
  tranif0 pmos_2(y, net_8, bb);
  tranif0 pmos_3(net_8, vdd, ab);
  tranif0 pmos_4(bb, vdd, b);
  tranif0 pmos_5(ab, vdd, a);
endmodule   /* muddlib07__xnor2_1x */

module memsys_final__comparator_20(a, b, y);
  input [19:0] a;
  input [19:0] b;
  output y;

  supply1 vdd;
  supply0 gnd;
  wire net_38, net_40;
  wire [19:0] y1;
  wire [4:0] y2;

  muddlib07__and2_1x and2_1x_0(.a(y2[1]), .b(y2[0]), .y(net_40));
  muddlib07__and2_1x and2_1x_1(.a(net_38), .b(net_40), .y(y));
  muddlib07__and3_1x and3_1x_0(.a(y2[4]), .b(y2[3]), .c(y2[2]), .y(net_38));
  muddlib07__and4_1x and4_4_(.a(y1[19]), .b(y1[18]), .c(y1[17]), .d(y1[16]), 
      .y(y2[4]));
  muddlib07__and4_1x and4_3_(.a(y1[15]), .b(y1[14]), .c(y1[13]), .d(y1[12]), 
      .y(y2[3]));
  muddlib07__and4_1x and4_2_(.a(y1[11]), .b(y1[10]), .c(y1[9]), .d(y1[8]), 
      .y(y2[2]));
  muddlib07__and4_1x and4_1_(.a(y1[7]), .b(y1[6]), .c(y1[5]), .d(y1[4]), 
      .y(y2[1]));
  muddlib07__and4_1x and4_0_(.a(y1[3]), .b(y1[2]), .c(y1[1]), .d(y1[0]), 
      .y(y2[0]));
  muddlib07__xnor2_1x xnor2_19_(.a(a[19]), .b(b[19]), .y(y1[19]));
  muddlib07__xnor2_1x xnor2_18_(.a(a[18]), .b(b[18]), .y(y1[18]));
  muddlib07__xnor2_1x xnor2_17_(.a(a[17]), .b(b[17]), .y(y1[17]));
  muddlib07__xnor2_1x xnor2_16_(.a(a[16]), .b(b[16]), .y(y1[16]));
  muddlib07__xnor2_1x xnor2_15_(.a(a[15]), .b(b[15]), .y(y1[15]));
  muddlib07__xnor2_1x xnor2_14_(.a(a[14]), .b(b[14]), .y(y1[14]));
  muddlib07__xnor2_1x xnor2_13_(.a(a[13]), .b(b[13]), .y(y1[13]));
  muddlib07__xnor2_1x xnor2_12_(.a(a[12]), .b(b[12]), .y(y1[12]));
  muddlib07__xnor2_1x xnor2_11_(.a(a[11]), .b(b[11]), .y(y1[11]));
  muddlib07__xnor2_1x xnor2_10_(.a(a[10]), .b(b[10]), .y(y1[10]));
  muddlib07__xnor2_1x xnor2_9_(.a(a[9]), .b(b[9]), .y(y1[9]));
  muddlib07__xnor2_1x xnor2_8_(.a(a[8]), .b(b[8]), .y(y1[8]));
  muddlib07__xnor2_1x xnor2_7_(.a(a[7]), .b(b[7]), .y(y1[7]));
  muddlib07__xnor2_1x xnor2_6_(.a(a[6]), .b(b[6]), .y(y1[6]));
  muddlib07__xnor2_1x xnor2_5_(.a(a[5]), .b(b[5]), .y(y1[5]));
  muddlib07__xnor2_1x xnor2_4_(.a(a[4]), .b(b[4]), .y(y1[4]));
  muddlib07__xnor2_1x xnor2_3_(.a(a[3]), .b(b[3]), .y(y1[3]));
  muddlib07__xnor2_1x xnor2_2_(.a(a[2]), .b(b[2]), .y(y1[2]));
  muddlib07__xnor2_1x xnor2_1_(.a(a[1]), .b(b[1]), .y(y1[1]));
  muddlib07__xnor2_1x xnor2_0_(.a(a[0]), .b(b[0]), .y(y1[0]));
endmodule   /* memsys_final__comparator_20 */

module muddlib07__or4_1x(a, b, c, d, y);
  input a;
  input b;
  input c;
  input d;
  output y;

  supply1 vdd;
  supply0 gnd;
  wire net_13, net_2, net_3, net_41;

  tranif1 nmos_0(gnd, net_13, d);
  tranif1 nmos_1(gnd, net_13, c);
  tranif1 nmos_2(gnd, net_13, b);
  tranif1 nmos_3(gnd, net_13, a);
  tranif1 nmos_4(gnd, y, net_13);
  tranif0 pmos_0(net_41, vdd, a);
  tranif0 pmos_1(net_2, net_41, b);
  tranif0 pmos_2(net_3, net_2, c);
  tranif0 pmos_3(net_13, net_3, d);
  tranif0 pmos_4(y, vdd, net_13);
endmodule   /* muddlib07__or4_1x */

module memsys_final__adrtagdatalogic(adr, adr_1, en, memdone, reset, rwb, 
      tagdata, valid, waiting, bypass, done);
  input [27:7] adr;
  input [29:29] adr_1;
  input en;
  input memdone;
  input reset;
  input rwb;
  input [19:0] tagdata;
  input valid;
  input waiting;
  output bypass;
  output done;

  supply1 vdd;
  supply0 gnd;
  wire bypass_b, en_b, incache, temp1, temp2, temp3;

  muddlib07__and2_1x and2_1x_0(.a(adr_1[29]), .b(adr[27]), .y(bypass));
  muddlib07__and2_1x and2_1x_1(.a(temp1), .b(valid), .y(incache));
  muddlib07__and2_1x and2_1x_2(.a(waiting), .b(memdone), .y(temp3));
  muddlib07__and3_1x and3_1x_0(.a(incache), .b(rwb), .c(bypass_b), .y(temp2));
  memsys_final__comparator_20 comparat_1(.a(tagdata[19:0]), .b(adr[26:7]), 
      .y(temp1));
  muddlib07__inv_1x inv_1x_0(.a(bypass), .y(bypass_b));
  muddlib07__inv_1x inv_1x_1(.a(en), .y(en_b));
  muddlib07__or4_1x or4_1x_0(.a(temp2), .b(en_b), .c(reset), .d(temp3), 
      .y(done));
endmodule   /* memsys_final__adrtagdatalogic */

module memsys_final__controllerstatelogic(done, memdone, rwb, s0, s1, nexts0, 
      nexts1);
  input done;
  input memdone;
  input rwb;
  input s0;
  input s1;
  output nexts0;
  output nexts1;

  supply1 vdd;
  supply0 gnd;
  wire done_b, memdone_b, net_0, net_5, net_54, net_7, net_83, s0_b, s1_b;

  muddlib07__and3_1x and3_1x_0(.a(s1), .b(s0_b), .c(memdone_b), .y(net_7));
  muddlib07__and3_1x and3_1x_1(.a(s1_b), .b(s0), .c(memdone_b), .y(net_5));
  muddlib07__and4_1x and4_1x_0(.a(s1_b), .b(s0_b), .c(net_54), .d(done_b), 
      .y(net_0));
  muddlib07__and4_1x and4_1x_1(.a(s1_b), .b(s0_b), .c(done_b), .d(rwb), 
      .y(net_83));
  muddlib07__inv_1x inv_1x_0(.a(s1), .y(s1_b));
  muddlib07__inv_1x inv_1x_1(.a(s0), .y(s0_b));
  muddlib07__inv_1x inv_1x_2(.a(done), .y(done_b));
  muddlib07__inv_1x inv_1x_3(.a(memdone), .y(memdone_b));
  muddlib07__inv_1x inv_1x_4(.a(rwb), .y(net_54));
  muddlib07__or2_1x or2_1x_0(.a(net_0), .b(net_7), .y(nexts1));
  muddlib07__or2_1x or2_1x_1(.a(net_5), .b(net_83), .y(nexts0));
endmodule   /* memsys_final__controllerstatelogic */

module muddlib07__flopr_c_1x(d, resetb, q, ph1, ph2);
  input d;
  input resetb;
  output q;
  input ph1;
  input ph2;

  supply1 vdd;
  supply0 gnd;
  wire master, masterinb, n6, n7, n8, n9, net_429, ph1b, ph1buf, ph2b, ph2buf;
  wire slaveb;
  trireg masterb, slave;

  tranif1 nmos_2(masterinb, masterb, ph2buf);
  tranif1 nmos_3(gnd, master, masterb);
  rtranif1 nmos_4(master, slave, ph1buf);
  tranif1 nmos_5(n6, masterb, ph2b);
  tranif1 nmos_6(gnd, n6, master);
  tranif1 nmos_7(gnd, n8, slaveb);
  tranif1 nmos_8(gnd, slaveb, slave);
  tranif1 nmos_10(n8, slave, ph1b);
  tranif1 nmos_11(gnd, q, slaveb);
  tranif1 nmos_17(gnd, net_429, resetb);
  tranif1 nmos_19(net_429, masterinb, d);
  tranif1 nmos_22(gnd, ph2b, ph2);
  tranif1 nmos_25(gnd, ph2buf, ph2b);
  tranif1 nmos_26(gnd, ph1buf, ph1b);
  tranif1 nmos_27(gnd, ph1b, ph1);
  tranif0 pmos_2(masterb, masterinb, ph2b);
  tranif0 pmos_3(master, vdd, masterb);
  rtranif0 pmos_4(slave, master, ph1b);
  tranif0 pmos_5(masterb, n7, ph2buf);
  tranif0 pmos_6(n7, vdd, master);
  tranif0 pmos_7(n9, vdd, slaveb);
  tranif0 pmos_8(slaveb, vdd, slave);
  tranif0 pmos_10(slave, n9, ph1buf);
  tranif0 pmos_11(q, vdd, slaveb);
  tranif0 pmos_16(masterinb, vdd, d);
  tranif0 pmos_18(masterinb, vdd, resetb);
  tranif0 pmos_21(ph1b, vdd, ph1);
  tranif0 pmos_22(ph2b, vdd, ph2);
  tranif0 pmos_24(ph1buf, vdd, ph1b);
  tranif0 pmos_25(ph2buf, vdd, ph2b);
endmodule   /* muddlib07__flopr_c_1x */

module memsys_final__cachecontroller(adr, adr_1, en, memdone, reset, rwb, 
      tagdata, valid, bypass, done, reading, waiting, ph1, ph2);
  input [27:7] adr;
  input [29:29] adr_1;
  input en;
  input memdone;
  input reset;
  input rwb;
  input [19:0] tagdata;
  input valid;
  output bypass;
  output done;
  output reading;
  output waiting;
  input ph1;
  input ph2;

  supply1 vdd;
  supply0 gnd;
  wire nextstate0, nextstate1, reset_b, state1;

  memsys_final__adrtagdatalogic adrtagda_4(.adr(adr[27:7]), 
      .adr_1(adr_1[29:29]), .en(en), .memdone(memdone), .reset(reset), 
      .rwb(rwb), .tagdata(tagdata[19:0]), .valid(valid), .waiting(waiting), 
      .bypass(bypass), .done(done));
  memsys_final__controllerstatelogic controll_3(.done(done), .memdone(memdone), 
      .rwb(rwb), .s0(reading), .s1(state1), .nexts0(nextstate0), 
      .nexts1(nextstate1));
  muddlib07__flopr_c_1x flopr_c__0(.d(nextstate1), .resetb(reset_b), 
      .q(state1), .ph1(ph1), .ph2(ph2));
  muddlib07__flopr_c_1x flopr_c__1(.d(nextstate0), .resetb(reset_b), 
      .q(reading), .ph1(ph1), .ph2(ph2));
  muddlib07__inv_1x inv_1x_2(.a(reset), .y(reset_b));
  muddlib07__or2_1x or2_1x_2(.a(state1), .b(reading), .y(waiting));
endmodule   /* memsys_final__cachecontroller */

module memsys_final__inv_32x(a, y);
  input a;
  output y;

  supply1 vdd;
  supply0 gnd;
  tranif1 nmos_0(gnd, y, a);
  tranif0 pmos_0(y, vdd, a);
endmodule   /* memsys_final__inv_32x */

module muddlib07__invbuf_4x(s, s_out, sb_out);
  input s;
  output s_out;
  output sb_out;

  supply1 vdd;
  supply0 gnd;
  muddlib07__inv_4x inv_4x_3(.a(s), .y(sb_out));
  muddlib07__inv_4x inv_4x_4(.a(sb_out), .y(s_out));
endmodule   /* muddlib07__invbuf_4x */

module memsys_final__cache_buffers(adr, ph1, ph2, rwb, word, adr_b, adr_buff, 
      ph1_b, ph1_bc_b, ph2_b, rwb_buff);
  input adr;
  input ph1;
  input ph2;
  input rwb;
  input [63:0] word;
  output adr_b;
  output adr_buff;
  output ph1_b;
  output ph1_bc_b;
  output ph2_b;
  output rwb_buff;

  supply1 vdd;
  supply0 gnd;
  wire invbuf_4_1_sb_out, invbuf_4_2_sb_out, net_113, net_49, net_58, net_59;
  wire net_61, net_66, net_69, net_79, net_99;

  muddlib07__inv_1x inv_1x_0(.a(adr_buff), .y(net_69));
  muddlib07__inv_1x inv_1x_1(.a(net_99), .y(net_59));
  muddlib07__inv_4x inv_4x_1(.a(net_113), .y(ph1_b));
  muddlib07__inv_4x inv_4x_2(.a(rwb), .y(net_49));
  muddlib07__inv_4x inv_4x_3(.a(net_59), .y(net_58));
  muddlib07__inv_4x inv_4x_4(.a(adr), .y(net_61));
  muddlib07__inv_4x inv_4x_5(.a(net_69), .y(net_66));
  memsys_final__inv_16x inv_8x_0(.a(ph1_b), .y(net_79));
  memsys_final__inv_32x inv_32x_0(.a(net_49), .y(rwb_buff));
  memsys_final__inv_32x inv_32x_1(.a(net_58), .y(ph2_b));
  memsys_final__inv_32x inv_32x_2(.a(net_61), .y(adr_buff));
  memsys_final__inv_32x inv_32x_3(.a(net_66), .y(adr_b));
  memsys_final__inv_64x inv_64x_0(.a(net_79), .y(ph1_bc_b));
  muddlib07__invbuf_4x invbuf_4_1(.s(ph2), .s_out(net_99), 
      .sb_out(invbuf_4_1_sb_out));
  muddlib07__invbuf_4x invbuf_4_2(.s(ph1), .s_out(net_113), 
      .sb_out(invbuf_4_2_sb_out));
endmodule   /* memsys_final__cache_buffers */

module memsys_final__bitconditioningkeeper(ph1_b, y1, y2);
  input ph1_b;
  output y1;
  output y2;

  supply1 vdd;
  supply0 gnd;
  tranif0 pmos_0(vdd, y1, ph1_b);
  tranif0 pmos_1(y2, vdd, ph1_b);
  rtranif0 pmos_2(y1, vdd, gnd);
  rtranif0 pmos_3(vdd, y2, gnd);
endmodule   /* memsys_final__bitconditioningkeeper */

module muddlib07__srambit(bit, bit_b, word);
  input bit;
  input bit_b;
  input word;

  supply1 vdd;
  supply0 gnd;
  wire net_67, net_68;

  tranif1 nmos_4(gnd, net_67, net_68);
  tranif1 nmos_5(net_68, gnd, net_67);
  tranif1 nmos_6(bit, net_68, word);
  tranif1 nmos_7(net_67, bit_b, word);
  rtranif0 pmos_2(net_67, vdd, net_68);
  rtranif0 pmos_3(vdd, net_68, net_67);
endmodule   /* muddlib07__srambit */

module memsys_final__writedriver(adr, adr_b, din, ph1_b, ph2_b, rwb, dataout, 
      y0, y1, y2, y3);
  input adr;
  input adr_b;
  input din;
  input ph1_b;
  input ph2_b;
  input rwb;
  output dataout;
  input y0;
  input y1;
  input y2;
  input y3;

  supply1 vdd;
  supply0 gnd;
  wire din_b, net_256, net_264, net_274, net_290, net_291, net_323;

  tranif1 nmos_22(gnd, net_256, ph2_b);
  tranif1 nmos_23(gnd, net_256, rwb);
  tranif1 nmos_24(gnd, net_256, din);
  tranif1 nmos_25(gnd, net_264, ph2_b);
  tranif1 nmos_26(gnd, net_264, rwb);
  tranif1 nmos_27(gnd, net_264, din_b);
  tranif1 nmos_28(gnd, net_274, net_256);
  tranif1 nmos_29(net_274, y0, adr);
  tranif1 nmos_30(net_274, y2, adr_b);
  tranif1 nmos_31(gnd, din_b, din);
  tranif1 nmos_32(gnd, net_323, net_264);
  tranif1 nmos_33(net_323, y3, adr_b);
  tranif1 nmos_34(net_323, y1, adr);
  tranif1 nmos_35(gnd, dataout, net_323);
  tranif0 pmos_13(din_b, vdd, din);
  tranif0 pmos_14(net_256, net_291, din);
  tranif0 pmos_15(net_291, net_290, rwb);
  tranif0 pmos_16(net_290, vdd, ph2_b);
  tranif0 pmos_17(net_264, net_291, din_b);
  tranif0 pmos_18(net_323, vdd, ph1_b);
  tranif0 pmos_19(dataout, vdd, net_323);
endmodule   /* memsys_final__writedriver */

module memsys_final__cacheramcolumn(adr, adr_b, din, rwb, word, dout, ph1_b, 
      ph1_b_buff, ph2_b);
  input adr;
  input adr_b;
  input din;
  input rwb;
  input [63:0] word;
  output dout;
  input ph1_b;
  input ph1_b_buff;
  input ph2_b;

  supply1 vdd;
  supply0 gnd;
  wire net_96, net_97, sram1bit, sram1bit_b;

  memsys_final__bitconditioningkeeper bitcondi_2(.ph1_b(ph1_b_buff), 
      .y1(sram1bit), .y2(sram1bit_b));
  memsys_final__bitconditioningkeeper bitcondi_3(.ph1_b(ph1_b_buff), 
      .y1(net_96), .y2(net_97));
  muddlib07__srambit srambit0_63_(.bit(net_97), .bit_b(net_96), 
      .word(word[63]));
  muddlib07__srambit srambit0_62_(.bit(net_97), .bit_b(net_96), 
      .word(word[62]));
  muddlib07__srambit srambit0_61_(.bit(net_97), .bit_b(net_96), 
      .word(word[61]));
  muddlib07__srambit srambit0_60_(.bit(net_97), .bit_b(net_96), 
      .word(word[60]));
  muddlib07__srambit srambit0_59_(.bit(net_97), .bit_b(net_96), 
      .word(word[59]));
  muddlib07__srambit srambit0_58_(.bit(net_97), .bit_b(net_96), 
      .word(word[58]));
  muddlib07__srambit srambit0_57_(.bit(net_97), .bit_b(net_96), 
      .word(word[57]));
  muddlib07__srambit srambit0_56_(.bit(net_97), .bit_b(net_96), 
      .word(word[56]));
  muddlib07__srambit srambit0_55_(.bit(net_97), .bit_b(net_96), 
      .word(word[55]));
  muddlib07__srambit srambit0_54_(.bit(net_97), .bit_b(net_96), 
      .word(word[54]));
  muddlib07__srambit srambit0_53_(.bit(net_97), .bit_b(net_96), 
      .word(word[53]));
  muddlib07__srambit srambit0_52_(.bit(net_97), .bit_b(net_96), 
      .word(word[52]));
  muddlib07__srambit srambit0_51_(.bit(net_97), .bit_b(net_96), 
      .word(word[51]));
  muddlib07__srambit srambit0_50_(.bit(net_97), .bit_b(net_96), 
      .word(word[50]));
  muddlib07__srambit srambit0_49_(.bit(net_97), .bit_b(net_96), 
      .word(word[49]));
  muddlib07__srambit srambit0_48_(.bit(net_97), .bit_b(net_96), 
      .word(word[48]));
  muddlib07__srambit srambit0_47_(.bit(net_97), .bit_b(net_96), 
      .word(word[47]));
  muddlib07__srambit srambit0_46_(.bit(net_97), .bit_b(net_96), 
      .word(word[46]));
  muddlib07__srambit srambit0_45_(.bit(net_97), .bit_b(net_96), 
      .word(word[45]));
  muddlib07__srambit srambit0_44_(.bit(net_97), .bit_b(net_96), 
      .word(word[44]));
  muddlib07__srambit srambit0_43_(.bit(net_97), .bit_b(net_96), 
      .word(word[43]));
  muddlib07__srambit srambit0_42_(.bit(net_97), .bit_b(net_96), 
      .word(word[42]));
  muddlib07__srambit srambit0_41_(.bit(net_97), .bit_b(net_96), 
      .word(word[41]));
  muddlib07__srambit srambit0_40_(.bit(net_97), .bit_b(net_96), 
      .word(word[40]));
  muddlib07__srambit srambit0_39_(.bit(net_97), .bit_b(net_96), 
      .word(word[39]));
  muddlib07__srambit srambit0_38_(.bit(net_97), .bit_b(net_96), 
      .word(word[38]));
  muddlib07__srambit srambit0_37_(.bit(net_97), .bit_b(net_96), 
      .word(word[37]));
  muddlib07__srambit srambit0_36_(.bit(net_97), .bit_b(net_96), 
      .word(word[36]));
  muddlib07__srambit srambit0_35_(.bit(net_97), .bit_b(net_96), 
      .word(word[35]));
  muddlib07__srambit srambit0_34_(.bit(net_97), .bit_b(net_96), 
      .word(word[34]));
  muddlib07__srambit srambit0_33_(.bit(net_97), .bit_b(net_96), 
      .word(word[33]));
  muddlib07__srambit srambit0_32_(.bit(net_97), .bit_b(net_96), 
      .word(word[32]));
  muddlib07__srambit srambit0_31_(.bit(net_97), .bit_b(net_96), 
      .word(word[31]));
  muddlib07__srambit srambit0_30_(.bit(net_97), .bit_b(net_96), 
      .word(word[30]));
  muddlib07__srambit srambit0_29_(.bit(net_97), .bit_b(net_96), 
      .word(word[29]));
  muddlib07__srambit srambit0_28_(.bit(net_97), .bit_b(net_96), 
      .word(word[28]));
  muddlib07__srambit srambit0_27_(.bit(net_97), .bit_b(net_96), 
      .word(word[27]));
  muddlib07__srambit srambit0_26_(.bit(net_97), .bit_b(net_96), 
      .word(word[26]));
  muddlib07__srambit srambit0_25_(.bit(net_97), .bit_b(net_96), 
      .word(word[25]));
  muddlib07__srambit srambit0_24_(.bit(net_97), .bit_b(net_96), 
      .word(word[24]));
  muddlib07__srambit srambit0_23_(.bit(net_97), .bit_b(net_96), 
      .word(word[23]));
  muddlib07__srambit srambit0_22_(.bit(net_97), .bit_b(net_96), 
      .word(word[22]));
  muddlib07__srambit srambit0_21_(.bit(net_97), .bit_b(net_96), 
      .word(word[21]));
  muddlib07__srambit srambit0_20_(.bit(net_97), .bit_b(net_96), 
      .word(word[20]));
  muddlib07__srambit srambit0_19_(.bit(net_97), .bit_b(net_96), 
      .word(word[19]));
  muddlib07__srambit srambit0_18_(.bit(net_97), .bit_b(net_96), 
      .word(word[18]));
  muddlib07__srambit srambit0_17_(.bit(net_97), .bit_b(net_96), 
      .word(word[17]));
  muddlib07__srambit srambit0_16_(.bit(net_97), .bit_b(net_96), 
      .word(word[16]));
  muddlib07__srambit srambit0_15_(.bit(net_97), .bit_b(net_96), 
      .word(word[15]));
  muddlib07__srambit srambit0_14_(.bit(net_97), .bit_b(net_96), 
      .word(word[14]));
  muddlib07__srambit srambit0_13_(.bit(net_97), .bit_b(net_96), 
      .word(word[13]));
  muddlib07__srambit srambit0_12_(.bit(net_97), .bit_b(net_96), 
      .word(word[12]));
  muddlib07__srambit srambit0_11_(.bit(net_97), .bit_b(net_96), 
      .word(word[11]));
  muddlib07__srambit srambit0_10_(.bit(net_97), .bit_b(net_96), 
      .word(word[10]));
  muddlib07__srambit srambit0_9_(.bit(net_97), .bit_b(net_96), 
      .word(word[9]));
  muddlib07__srambit srambit0_8_(.bit(net_97), .bit_b(net_96), 
      .word(word[8]));
  muddlib07__srambit srambit0_7_(.bit(net_97), .bit_b(net_96), 
      .word(word[7]));
  muddlib07__srambit srambit0_6_(.bit(net_97), .bit_b(net_96), 
      .word(word[6]));
  muddlib07__srambit srambit0_5_(.bit(net_97), .bit_b(net_96), 
      .word(word[5]));
  muddlib07__srambit srambit0_4_(.bit(net_97), .bit_b(net_96), 
      .word(word[4]));
  muddlib07__srambit srambit0_3_(.bit(net_97), .bit_b(net_96), 
      .word(word[3]));
  muddlib07__srambit srambit0_2_(.bit(net_97), .bit_b(net_96), 
      .word(word[2]));
  muddlib07__srambit srambit0_1_(.bit(net_97), .bit_b(net_96), 
      .word(word[1]));
  muddlib07__srambit srambit0_0_(.bit(net_97), .bit_b(net_96), 
      .word(word[0]));
  muddlib07__srambit srambit1_63_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[63]));
  muddlib07__srambit srambit1_62_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[62]));
  muddlib07__srambit srambit1_61_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[61]));
  muddlib07__srambit srambit1_60_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[60]));
  muddlib07__srambit srambit1_59_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[59]));
  muddlib07__srambit srambit1_58_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[58]));
  muddlib07__srambit srambit1_57_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[57]));
  muddlib07__srambit srambit1_56_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[56]));
  muddlib07__srambit srambit1_55_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[55]));
  muddlib07__srambit srambit1_54_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[54]));
  muddlib07__srambit srambit1_53_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[53]));
  muddlib07__srambit srambit1_52_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[52]));
  muddlib07__srambit srambit1_51_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[51]));
  muddlib07__srambit srambit1_50_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[50]));
  muddlib07__srambit srambit1_49_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[49]));
  muddlib07__srambit srambit1_48_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[48]));
  muddlib07__srambit srambit1_47_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[47]));
  muddlib07__srambit srambit1_46_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[46]));
  muddlib07__srambit srambit1_45_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[45]));
  muddlib07__srambit srambit1_44_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[44]));
  muddlib07__srambit srambit1_43_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[43]));
  muddlib07__srambit srambit1_42_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[42]));
  muddlib07__srambit srambit1_41_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[41]));
  muddlib07__srambit srambit1_40_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[40]));
  muddlib07__srambit srambit1_39_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[39]));
  muddlib07__srambit srambit1_38_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[38]));
  muddlib07__srambit srambit1_37_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[37]));
  muddlib07__srambit srambit1_36_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[36]));
  muddlib07__srambit srambit1_35_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[35]));
  muddlib07__srambit srambit1_34_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[34]));
  muddlib07__srambit srambit1_33_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[33]));
  muddlib07__srambit srambit1_32_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[32]));
  muddlib07__srambit srambit1_31_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[31]));
  muddlib07__srambit srambit1_30_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[30]));
  muddlib07__srambit srambit1_29_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[29]));
  muddlib07__srambit srambit1_28_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[28]));
  muddlib07__srambit srambit1_27_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[27]));
  muddlib07__srambit srambit1_26_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[26]));
  muddlib07__srambit srambit1_25_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[25]));
  muddlib07__srambit srambit1_24_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[24]));
  muddlib07__srambit srambit1_23_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[23]));
  muddlib07__srambit srambit1_22_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[22]));
  muddlib07__srambit srambit1_21_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[21]));
  muddlib07__srambit srambit1_20_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[20]));
  muddlib07__srambit srambit1_19_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[19]));
  muddlib07__srambit srambit1_18_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[18]));
  muddlib07__srambit srambit1_17_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[17]));
  muddlib07__srambit srambit1_16_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[16]));
  muddlib07__srambit srambit1_15_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[15]));
  muddlib07__srambit srambit1_14_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[14]));
  muddlib07__srambit srambit1_13_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[13]));
  muddlib07__srambit srambit1_12_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[12]));
  muddlib07__srambit srambit1_11_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[11]));
  muddlib07__srambit srambit1_10_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[10]));
  muddlib07__srambit srambit1_9_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[9]));
  muddlib07__srambit srambit1_8_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[8]));
  muddlib07__srambit srambit1_7_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[7]));
  muddlib07__srambit srambit1_6_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[6]));
  muddlib07__srambit srambit1_5_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[5]));
  muddlib07__srambit srambit1_4_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[4]));
  muddlib07__srambit srambit1_3_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[3]));
  muddlib07__srambit srambit1_2_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[2]));
  muddlib07__srambit srambit1_1_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[1]));
  muddlib07__srambit srambit1_0_(.bit(sram1bit), .bit_b(sram1bit_b), 
      .word(word[0]));
  memsys_final__writedriver writedri_4(.adr(adr), .adr_b(adr_b), .din(din), 
      .ph1_b(ph1_b), .ph2_b(ph2_b), .rwb(rwb), .dataout(dout), .y0(sram1bit), 
      .y1(sram1bit_b), .y2(net_96), .y3(net_97));
endmodule   /* memsys_final__cacheramcolumn */

module memsys_final__cacheramarray(adr, adr_b, din, ph1_b, ph1_b_buff, ph2_b, 
      rwb, word, dout);
  input adr;
  input adr_b;
  input [52:0] din;
  input ph1_b;
  input ph1_b_buff;
  input ph2_b;
  input rwb;
  input [63:0] word;
  output [52:0] dout;

  supply1 vdd;
  supply0 gnd;
  memsys_final__cacheramcolumn cacheramcolumn_52_(.adr(adr), .adr_b(adr_b), 
      .din(din[52]), .rwb(rwb), .word(word[63:0]), .dout(dout[52]), 
      .ph1_b(ph1_b), .ph1_b_buff(ph1_b_buff), .ph2_b(ph2_b));
  memsys_final__cacheramcolumn cacheramcolumn_51_(.adr(adr), .adr_b(adr_b), 
      .din(din[51]), .rwb(rwb), .word(word[63:0]), .dout(dout[51]), 
      .ph1_b(ph1_b), .ph1_b_buff(ph1_b_buff), .ph2_b(ph2_b));
  memsys_final__cacheramcolumn cacheramcolumn_50_(.adr(adr), .adr_b(adr_b), 
      .din(din[50]), .rwb(rwb), .word(word[63:0]), .dout(dout[50]), 
      .ph1_b(ph1_b), .ph1_b_buff(ph1_b_buff), .ph2_b(ph2_b));
  memsys_final__cacheramcolumn cacheramcolumn_49_(.adr(adr), .adr_b(adr_b), 
      .din(din[49]), .rwb(rwb), .word(word[63:0]), .dout(dout[49]), 
      .ph1_b(ph1_b), .ph1_b_buff(ph1_b_buff), .ph2_b(ph2_b));
  memsys_final__cacheramcolumn cacheramcolumn_48_(.adr(adr), .adr_b(adr_b), 
      .din(din[48]), .rwb(rwb), .word(word[63:0]), .dout(dout[48]), 
      .ph1_b(ph1_b), .ph1_b_buff(ph1_b_buff), .ph2_b(ph2_b));
  memsys_final__cacheramcolumn cacheramcolumn_47_(.adr(adr), .adr_b(adr_b), 
      .din(din[47]), .rwb(rwb), .word(word[63:0]), .dout(dout[47]), 
      .ph1_b(ph1_b), .ph1_b_buff(ph1_b_buff), .ph2_b(ph2_b));
  memsys_final__cacheramcolumn cacheramcolumn_46_(.adr(adr), .adr_b(adr_b), 
      .din(din[46]), .rwb(rwb), .word(word[63:0]), .dout(dout[46]), 
      .ph1_b(ph1_b), .ph1_b_buff(ph1_b_buff), .ph2_b(ph2_b));
  memsys_final__cacheramcolumn cacheramcolumn_45_(.adr(adr), .adr_b(adr_b), 
      .din(din[45]), .rwb(rwb), .word(word[63:0]), .dout(dout[45]), 
      .ph1_b(ph1_b), .ph1_b_buff(ph1_b_buff), .ph2_b(ph2_b));
  memsys_final__cacheramcolumn cacheramcolumn_44_(.adr(adr), .adr_b(adr_b), 
      .din(din[44]), .rwb(rwb), .word(word[63:0]), .dout(dout[44]), 
      .ph1_b(ph1_b), .ph1_b_buff(ph1_b_buff), .ph2_b(ph2_b));
  memsys_final__cacheramcolumn cacheramcolumn_43_(.adr(adr), .adr_b(adr_b), 
      .din(din[43]), .rwb(rwb), .word(word[63:0]), .dout(dout[43]), 
      .ph1_b(ph1_b), .ph1_b_buff(ph1_b_buff), .ph2_b(ph2_b));
  memsys_final__cacheramcolumn cacheramcolumn_42_(.adr(adr), .adr_b(adr_b), 
      .din(din[42]), .rwb(rwb), .word(word[63:0]), .dout(dout[42]), 
      .ph1_b(ph1_b), .ph1_b_buff(ph1_b_buff), .ph2_b(ph2_b));
  memsys_final__cacheramcolumn cacheramcolumn_41_(.adr(adr), .adr_b(adr_b), 
      .din(din[41]), .rwb(rwb), .word(word[63:0]), .dout(dout[41]), 
      .ph1_b(ph1_b), .ph1_b_buff(ph1_b_buff), .ph2_b(ph2_b));
  memsys_final__cacheramcolumn cacheramcolumn_40_(.adr(adr), .adr_b(adr_b), 
      .din(din[40]), .rwb(rwb), .word(word[63:0]), .dout(dout[40]), 
      .ph1_b(ph1_b), .ph1_b_buff(ph1_b_buff), .ph2_b(ph2_b));
  memsys_final__cacheramcolumn cacheramcolumn_39_(.adr(adr), .adr_b(adr_b), 
      .din(din[39]), .rwb(rwb), .word(word[63:0]), .dout(dout[39]), 
      .ph1_b(ph1_b), .ph1_b_buff(ph1_b_buff), .ph2_b(ph2_b));
  memsys_final__cacheramcolumn cacheramcolumn_38_(.adr(adr), .adr_b(adr_b), 
      .din(din[38]), .rwb(rwb), .word(word[63:0]), .dout(dout[38]), 
      .ph1_b(ph1_b), .ph1_b_buff(ph1_b_buff), .ph2_b(ph2_b));
  memsys_final__cacheramcolumn cacheramcolumn_37_(.adr(adr), .adr_b(adr_b), 
      .din(din[37]), .rwb(rwb), .word(word[63:0]), .dout(dout[37]), 
      .ph1_b(ph1_b), .ph1_b_buff(ph1_b_buff), .ph2_b(ph2_b));
  memsys_final__cacheramcolumn cacheramcolumn_36_(.adr(adr), .adr_b(adr_b), 
      .din(din[36]), .rwb(rwb), .word(word[63:0]), .dout(dout[36]), 
      .ph1_b(ph1_b), .ph1_b_buff(ph1_b_buff), .ph2_b(ph2_b));
  memsys_final__cacheramcolumn cacheramcolumn_35_(.adr(adr), .adr_b(adr_b), 
      .din(din[35]), .rwb(rwb), .word(word[63:0]), .dout(dout[35]), 
      .ph1_b(ph1_b), .ph1_b_buff(ph1_b_buff), .ph2_b(ph2_b));
  memsys_final__cacheramcolumn cacheramcolumn_34_(.adr(adr), .adr_b(adr_b), 
      .din(din[34]), .rwb(rwb), .word(word[63:0]), .dout(dout[34]), 
      .ph1_b(ph1_b), .ph1_b_buff(ph1_b_buff), .ph2_b(ph2_b));
  memsys_final__cacheramcolumn cacheramcolumn_33_(.adr(adr), .adr_b(adr_b), 
      .din(din[33]), .rwb(rwb), .word(word[63:0]), .dout(dout[33]), 
      .ph1_b(ph1_b), .ph1_b_buff(ph1_b_buff), .ph2_b(ph2_b));
  memsys_final__cacheramcolumn cacheramcolumn_32_(.adr(adr), .adr_b(adr_b), 
      .din(din[32]), .rwb(rwb), .word(word[63:0]), .dout(dout[32]), 
      .ph1_b(ph1_b), .ph1_b_buff(ph1_b_buff), .ph2_b(ph2_b));
  memsys_final__cacheramcolumn cacheramcolumn_31_(.adr(adr), .adr_b(adr_b), 
      .din(din[31]), .rwb(rwb), .word(word[63:0]), .dout(dout[31]), 
      .ph1_b(ph1_b), .ph1_b_buff(ph1_b_buff), .ph2_b(ph2_b));
  memsys_final__cacheramcolumn cacheramcolumn_30_(.adr(adr), .adr_b(adr_b), 
      .din(din[30]), .rwb(rwb), .word(word[63:0]), .dout(dout[30]), 
      .ph1_b(ph1_b), .ph1_b_buff(ph1_b_buff), .ph2_b(ph2_b));
  memsys_final__cacheramcolumn cacheramcolumn_29_(.adr(adr), .adr_b(adr_b), 
      .din(din[29]), .rwb(rwb), .word(word[63:0]), .dout(dout[29]), 
      .ph1_b(ph1_b), .ph1_b_buff(ph1_b_buff), .ph2_b(ph2_b));
  memsys_final__cacheramcolumn cacheramcolumn_28_(.adr(adr), .adr_b(adr_b), 
      .din(din[28]), .rwb(rwb), .word(word[63:0]), .dout(dout[28]), 
      .ph1_b(ph1_b), .ph1_b_buff(ph1_b_buff), .ph2_b(ph2_b));
  memsys_final__cacheramcolumn cacheramcolumn_27_(.adr(adr), .adr_b(adr_b), 
      .din(din[27]), .rwb(rwb), .word(word[63:0]), .dout(dout[27]), 
      .ph1_b(ph1_b), .ph1_b_buff(ph1_b_buff), .ph2_b(ph2_b));
  memsys_final__cacheramcolumn cacheramcolumn_26_(.adr(adr), .adr_b(adr_b), 
      .din(din[26]), .rwb(rwb), .word(word[63:0]), .dout(dout[26]), 
      .ph1_b(ph1_b), .ph1_b_buff(ph1_b_buff), .ph2_b(ph2_b));
  memsys_final__cacheramcolumn cacheramcolumn_25_(.adr(adr), .adr_b(adr_b), 
      .din(din[25]), .rwb(rwb), .word(word[63:0]), .dout(dout[25]), 
      .ph1_b(ph1_b), .ph1_b_buff(ph1_b_buff), .ph2_b(ph2_b));
  memsys_final__cacheramcolumn cacheramcolumn_24_(.adr(adr), .adr_b(adr_b), 
      .din(din[24]), .rwb(rwb), .word(word[63:0]), .dout(dout[24]), 
      .ph1_b(ph1_b), .ph1_b_buff(ph1_b_buff), .ph2_b(ph2_b));
  memsys_final__cacheramcolumn cacheramcolumn_23_(.adr(adr), .adr_b(adr_b), 
      .din(din[23]), .rwb(rwb), .word(word[63:0]), .dout(dout[23]), 
      .ph1_b(ph1_b), .ph1_b_buff(ph1_b_buff), .ph2_b(ph2_b));
  memsys_final__cacheramcolumn cacheramcolumn_22_(.adr(adr), .adr_b(adr_b), 
      .din(din[22]), .rwb(rwb), .word(word[63:0]), .dout(dout[22]), 
      .ph1_b(ph1_b), .ph1_b_buff(ph1_b_buff), .ph2_b(ph2_b));
  memsys_final__cacheramcolumn cacheramcolumn_21_(.adr(adr), .adr_b(adr_b), 
      .din(din[21]), .rwb(rwb), .word(word[63:0]), .dout(dout[21]), 
      .ph1_b(ph1_b), .ph1_b_buff(ph1_b_buff), .ph2_b(ph2_b));
  memsys_final__cacheramcolumn cacheramcolumn_20_(.adr(adr), .adr_b(adr_b), 
      .din(din[20]), .rwb(rwb), .word(word[63:0]), .dout(dout[20]), 
      .ph1_b(ph1_b), .ph1_b_buff(ph1_b_buff), .ph2_b(ph2_b));
  memsys_final__cacheramcolumn cacheramcolumn_19_(.adr(adr), .adr_b(adr_b), 
      .din(din[19]), .rwb(rwb), .word(word[63:0]), .dout(dout[19]), 
      .ph1_b(ph1_b), .ph1_b_buff(ph1_b_buff), .ph2_b(ph2_b));
  memsys_final__cacheramcolumn cacheramcolumn_18_(.adr(adr), .adr_b(adr_b), 
      .din(din[18]), .rwb(rwb), .word(word[63:0]), .dout(dout[18]), 
      .ph1_b(ph1_b), .ph1_b_buff(ph1_b_buff), .ph2_b(ph2_b));
  memsys_final__cacheramcolumn cacheramcolumn_17_(.adr(adr), .adr_b(adr_b), 
      .din(din[17]), .rwb(rwb), .word(word[63:0]), .dout(dout[17]), 
      .ph1_b(ph1_b), .ph1_b_buff(ph1_b_buff), .ph2_b(ph2_b));
  memsys_final__cacheramcolumn cacheramcolumn_16_(.adr(adr), .adr_b(adr_b), 
      .din(din[16]), .rwb(rwb), .word(word[63:0]), .dout(dout[16]), 
      .ph1_b(ph1_b), .ph1_b_buff(ph1_b_buff), .ph2_b(ph2_b));
  memsys_final__cacheramcolumn cacheramcolumn_15_(.adr(adr), .adr_b(adr_b), 
      .din(din[15]), .rwb(rwb), .word(word[63:0]), .dout(dout[15]), 
      .ph1_b(ph1_b), .ph1_b_buff(ph1_b_buff), .ph2_b(ph2_b));
  memsys_final__cacheramcolumn cacheramcolumn_14_(.adr(adr), .adr_b(adr_b), 
      .din(din[14]), .rwb(rwb), .word(word[63:0]), .dout(dout[14]), 
      .ph1_b(ph1_b), .ph1_b_buff(ph1_b_buff), .ph2_b(ph2_b));
  memsys_final__cacheramcolumn cacheramcolumn_13_(.adr(adr), .adr_b(adr_b), 
      .din(din[13]), .rwb(rwb), .word(word[63:0]), .dout(dout[13]), 
      .ph1_b(ph1_b), .ph1_b_buff(ph1_b_buff), .ph2_b(ph2_b));
  memsys_final__cacheramcolumn cacheramcolumn_12_(.adr(adr), .adr_b(adr_b), 
      .din(din[12]), .rwb(rwb), .word(word[63:0]), .dout(dout[12]), 
      .ph1_b(ph1_b), .ph1_b_buff(ph1_b_buff), .ph2_b(ph2_b));
  memsys_final__cacheramcolumn cacheramcolumn_11_(.adr(adr), .adr_b(adr_b), 
      .din(din[11]), .rwb(rwb), .word(word[63:0]), .dout(dout[11]), 
      .ph1_b(ph1_b), .ph1_b_buff(ph1_b_buff), .ph2_b(ph2_b));
  memsys_final__cacheramcolumn cacheramcolumn_10_(.adr(adr), .adr_b(adr_b), 
      .din(din[10]), .rwb(rwb), .word(word[63:0]), .dout(dout[10]), 
      .ph1_b(ph1_b), .ph1_b_buff(ph1_b_buff), .ph2_b(ph2_b));
  memsys_final__cacheramcolumn cacheramcolumn_9_(.adr(adr), .adr_b(adr_b), 
      .din(din[9]), .rwb(rwb), .word(word[63:0]), .dout(dout[9]), 
      .ph1_b(ph1_b), .ph1_b_buff(ph1_b_buff), .ph2_b(ph2_b));
  memsys_final__cacheramcolumn cacheramcolumn_8_(.adr(adr), .adr_b(adr_b), 
      .din(din[8]), .rwb(rwb), .word(word[63:0]), .dout(dout[8]), 
      .ph1_b(ph1_b), .ph1_b_buff(ph1_b_buff), .ph2_b(ph2_b));
  memsys_final__cacheramcolumn cacheramcolumn_7_(.adr(adr), .adr_b(adr_b), 
      .din(din[7]), .rwb(rwb), .word(word[63:0]), .dout(dout[7]), 
      .ph1_b(ph1_b), .ph1_b_buff(ph1_b_buff), .ph2_b(ph2_b));
  memsys_final__cacheramcolumn cacheramcolumn_6_(.adr(adr), .adr_b(adr_b), 
      .din(din[6]), .rwb(rwb), .word(word[63:0]), .dout(dout[6]), 
      .ph1_b(ph1_b), .ph1_b_buff(ph1_b_buff), .ph2_b(ph2_b));
  memsys_final__cacheramcolumn cacheramcolumn_5_(.adr(adr), .adr_b(adr_b), 
      .din(din[5]), .rwb(rwb), .word(word[63:0]), .dout(dout[5]), 
      .ph1_b(ph1_b), .ph1_b_buff(ph1_b_buff), .ph2_b(ph2_b));
  memsys_final__cacheramcolumn cacheramcolumn_4_(.adr(adr), .adr_b(adr_b), 
      .din(din[4]), .rwb(rwb), .word(word[63:0]), .dout(dout[4]), 
      .ph1_b(ph1_b), .ph1_b_buff(ph1_b_buff), .ph2_b(ph2_b));
  memsys_final__cacheramcolumn cacheramcolumn_3_(.adr(adr), .adr_b(adr_b), 
      .din(din[3]), .rwb(rwb), .word(word[63:0]), .dout(dout[3]), 
      .ph1_b(ph1_b), .ph1_b_buff(ph1_b_buff), .ph2_b(ph2_b));
  memsys_final__cacheramcolumn cacheramcolumn_2_(.adr(adr), .adr_b(adr_b), 
      .din(din[2]), .rwb(rwb), .word(word[63:0]), .dout(dout[2]), 
      .ph1_b(ph1_b), .ph1_b_buff(ph1_b_buff), .ph2_b(ph2_b));
  memsys_final__cacheramcolumn cacheramcolumn_1_(.adr(adr), .adr_b(adr_b), 
      .din(din[1]), .rwb(rwb), .word(word[63:0]), .dout(dout[1]), 
      .ph1_b(ph1_b), .ph1_b_buff(ph1_b_buff), .ph2_b(ph2_b));
  memsys_final__cacheramcolumn cacheramcolumn_0_(.adr(adr), .adr_b(adr_b), 
      .din(din[0]), .rwb(rwb), .word(word[63:0]), .dout(dout[0]), 
      .ph1_b(ph1_b), .ph1_b_buff(ph1_b_buff), .ph2_b(ph2_b));
endmodule   /* memsys_final__cacheramarray */

module muddlib07__inv_2x(a, y);
  input a;
  output y;

  supply1 vdd;
  supply0 gnd;
  tranif1 nmos_0(gnd, y, a);
  tranif0 pmos_0(y, vdd, a);
endmodule   /* muddlib07__inv_2x */

module memsys_final__nand2_4x(a, b, y);
  input a;
  input b;
  output y;

  supply1 vdd;
  supply0 gnd;
  wire net_42, net_5;

  tranif1 nmos_0(net_5, y, b);
  tranif1 nmos_1(gnd, net_5, a);
  tranif1 nmos_2(net_42, y, b);
  tranif1 nmos_3(gnd, net_42, a);
  tranif0 pmos_0(y, vdd, b);
  tranif0 pmos_1(y, vdd, a);
  tranif0 pmos_2(y, vdd, b);
  tranif0 pmos_3(y, vdd, a);
endmodule   /* memsys_final__nand2_4x */

module memsys_final__nand3_2x(a, b, c, y);
  input a;
  input b;
  input c;
  output y;

  supply1 vdd;
  supply0 gnd;
  wire net_15, net_4;

  tranif1 nmos_0(net_15, net_4, b);
  tranif1 nmos_1(net_4, y, a);
  tranif1 nmos_2(gnd, net_15, c);
  tranif0 pmos_0(y, vdd, a);
  tranif0 pmos_1(y, vdd, b);
  tranif0 pmos_2(y, vdd, c);
endmodule   /* memsys_final__nand3_2x */

module muddlib07__nand2_1x(a, b, y);
  input a;
  input b;
  output y;

  supply1 vdd;
  supply0 gnd;
  wire net_5;

  tranif1 nmos_0(net_5, y, b);
  tranif1 nmos_1(gnd, net_5, a);
  tranif0 pmos_0(y, vdd, b);
  tranif0 pmos_1(y, vdd, a);
endmodule   /* muddlib07__nand2_1x */

module memsys_final__decoder64b(a, ph2, y);
  input [5:0] a;
  input ph2;
  output [63:0] y;

  supply1 vdd;
  supply0 gnd;
  wire a0_b, a0buf, a1_b, a1buf, a2_b, a2buf, a3_b, a3buf, a4_b, a4buf, a5_b;
  wire a5buf, c0, c1, c2, c3, c4, c5, c6, c7, d0, d1, d2, d3, d4, d5, d6, d7;
  wire net_1085, net_1086, net_1087, net_1088, net_1089, net_1090, net_1091;
  wire net_1092, net_1093, net_1094, net_1095, net_1096, net_1314, net_1315;
  wire net_1316, net_1317, net_1318, net_1319, net_1320, net_1321, net_1322;
  wire net_1323, net_1324, net_1325, net_1326, net_1327, net_1328, net_1329;
  wire net_1330, net_1331, net_1332, net_1333, net_1334, net_1335, net_1336;
  wire net_1337, net_1338, net_1339, net_1340, net_1341, net_1342, net_1343;
  wire net_1344, net_1345, net_1346, net_1347, net_1348, net_1349, net_1350;
  wire net_1351, net_1352, net_1353, net_1354, net_1355, net_1356, net_1357;
  wire net_1358, net_1359, net_1360, net_1361, net_1362, net_1363, net_1364;
  wire net_1365, net_1366, net_1367, net_1368, net_1369, net_1370, net_1371;
  wire net_1372, net_1373, net_1374, net_1375, net_1376, net_1377, net_1378;
  wire net_1379, net_1380, net_1381, net_1382, net_1383, net_1384, net_1385;
  wire net_1386, net_1387, net_1388, net_1389, net_1390, net_1391, net_1392;
  wire net_1393, net_1394, net_1395, net_1396, net_1397, net_1398, net_1399;
  wire net_1400, net_1401, net_1402, net_1403, net_1404, net_1405, net_1406;
  wire net_1407, net_1408, net_1409, net_1410, net_1411, net_1412, net_1413;
  wire net_1414, net_1415, net_1416, net_1417, net_1418, net_1419, net_1420;
  wire net_1421, net_1422, net_1423, net_1424, net_1425, net_1426, net_1427;
  wire net_1428, net_1429, net_1430, net_1431, net_1432, net_1433, net_1434;
  wire net_1435, net_1436, net_1437, net_1438, net_1439, net_1440, net_1441;
  wire net_1442, net_1443, net_1444, net_1445, net_1446, net_1447, net_1448;
  wire net_1449, net_1450, net_1451, net_1452, net_1453, net_1454, net_1455;
  wire net_1456, net_1457, net_1458, net_1459, net_1460, net_1461, net_1462;
  wire net_1463, net_1464, net_1465, net_1466, net_1467, net_1468, net_1469;
  wire net_1470, net_1471, net_1472, net_1473, net_1474, net_1475, net_1476;
  wire net_1477, net_1478, net_1479, net_1480, net_1481, net_1482, net_1483;
  wire net_1484, net_1485, net_1486, net_1487, net_1488, net_1489, net_1490;
  wire net_1491, net_1492, net_1493, net_1494, net_1495, net_1496, net_1497;
  wire net_1498, net_1499, net_1500, net_1501, net_1502, net_1503, net_1504;
  wire net_1505, net_1570, net_1571, net_1572, net_1573, net_1574, net_1575;
  wire net_1576, net_1577, net_1578, net_1579, net_1580, net_1581, net_1582;
  wire net_1583, net_1584, net_1585, net_1586, net_1587, net_1588, net_1589;
  wire net_1590, net_1591, net_1592, net_1593, net_1594, net_1595, net_1596;
  wire net_1597, net_1598, net_1599, net_1600, net_1601, net_1602, net_1603;
  wire net_1604, net_1605, net_1606, net_1607, net_1608, net_1609, net_1610;
  wire net_1611, net_1612, net_1613, net_1614, net_1615, net_1616, net_1617;
  wire net_1618, net_1619, net_1620, net_1621, net_1622, net_1623, net_1624;
  wire net_1625, net_1626, net_1627, net_1628, net_1629, net_1630, net_1631;
  wire net_1632, net_1633, net_1634, net_1635, net_1636, net_758, net_759;
  wire net_761, ph1_sb_out;

  muddlib07__inv_1x inv_1x_0(.a(net_1636), .y(net_1442));
  muddlib07__inv_1x inv_1x_1(.a(net_1636), .y(net_1443));
  muddlib07__inv_1x inv_1x_2(.a(net_1636), .y(net_1444));
  muddlib07__inv_1x inv_1x_3(.a(net_1636), .y(net_1445));
  muddlib07__inv_1x inv_1x_4(.a(net_1636), .y(net_1446));
  muddlib07__inv_1x inv_1x_5(.a(net_1636), .y(net_1447));
  muddlib07__inv_1x inv_1x_6(.a(net_1636), .y(net_1448));
  muddlib07__inv_1x inv_1x_7(.a(net_1636), .y(net_1449));
  muddlib07__inv_1x inv_1x_8(.a(net_1636), .y(net_1450));
  muddlib07__inv_1x inv_1x_9(.a(net_1636), .y(net_1451));
  muddlib07__inv_1x inv_1x_10(.a(net_1636), .y(net_1452));
  muddlib07__inv_1x inv_1x_11(.a(net_1636), .y(net_1453));
  muddlib07__inv_1x inv_1x_12(.a(net_1636), .y(net_1454));
  muddlib07__inv_1x inv_1x_13(.a(net_1636), .y(net_1455));
  muddlib07__inv_1x inv_1x_14(.a(net_1636), .y(net_1456));
  muddlib07__inv_1x inv_1x_15(.a(net_1636), .y(net_1457));
  muddlib07__inv_1x inv_1x_16(.a(net_1636), .y(net_1458));
  muddlib07__inv_1x inv_1x_17(.a(net_1636), .y(net_1459));
  muddlib07__inv_1x inv_1x_18(.a(net_1636), .y(net_1460));
  muddlib07__inv_1x inv_1x_19(.a(net_1636), .y(net_1461));
  muddlib07__inv_1x inv_1x_20(.a(net_1636), .y(net_1462));
  muddlib07__inv_1x inv_1x_21(.a(net_1636), .y(net_1463));
  muddlib07__inv_1x inv_1x_22(.a(net_1636), .y(net_1464));
  muddlib07__inv_1x inv_1x_23(.a(net_1636), .y(net_1465));
  muddlib07__inv_1x inv_1x_24(.a(net_1636), .y(net_1466));
  muddlib07__inv_1x inv_1x_25(.a(net_1636), .y(net_1467));
  muddlib07__inv_1x inv_1x_26(.a(net_1636), .y(net_1468));
  muddlib07__inv_1x inv_1x_27(.a(net_1636), .y(net_1469));
  muddlib07__inv_1x inv_1x_28(.a(net_1636), .y(net_1470));
  muddlib07__inv_1x inv_1x_29(.a(net_1636), .y(net_1471));
  muddlib07__inv_1x inv_1x_30(.a(net_1636), .y(net_1472));
  muddlib07__inv_1x inv_1x_31(.a(net_1636), .y(net_1473));
  muddlib07__inv_1x inv_1x_32(.a(net_1636), .y(net_1474));
  muddlib07__inv_1x inv_1x_33(.a(net_1636), .y(net_1475));
  muddlib07__inv_1x inv_1x_34(.a(net_1636), .y(net_1476));
  muddlib07__inv_1x inv_1x_35(.a(net_1636), .y(net_1477));
  muddlib07__inv_1x inv_1x_36(.a(net_1636), .y(net_1478));
  muddlib07__inv_1x inv_1x_37(.a(net_1636), .y(net_1479));
  muddlib07__inv_1x inv_1x_38(.a(net_1636), .y(net_1480));
  muddlib07__inv_1x inv_1x_39(.a(net_1636), .y(net_1481));
  muddlib07__inv_1x inv_1x_40(.a(net_1636), .y(net_1482));
  muddlib07__inv_1x inv_1x_41(.a(net_1636), .y(net_1483));
  muddlib07__inv_1x inv_1x_42(.a(net_1636), .y(net_1484));
  muddlib07__inv_1x inv_1x_43(.a(net_1636), .y(net_1485));
  muddlib07__inv_1x inv_1x_44(.a(net_1636), .y(net_1486));
  muddlib07__inv_1x inv_1x_45(.a(net_1636), .y(net_1487));
  muddlib07__inv_1x inv_1x_46(.a(net_1636), .y(net_1488));
  muddlib07__inv_1x inv_1x_47(.a(net_1636), .y(net_1489));
  muddlib07__inv_1x inv_1x_48(.a(net_1636), .y(net_1490));
  muddlib07__inv_1x inv_1x_49(.a(net_1636), .y(net_1491));
  muddlib07__inv_1x inv_1x_50(.a(net_1636), .y(net_1492));
  muddlib07__inv_1x inv_1x_51(.a(net_1636), .y(net_1493));
  muddlib07__inv_1x inv_1x_52(.a(net_1636), .y(net_1494));
  muddlib07__inv_1x inv_1x_53(.a(net_1636), .y(net_1495));
  muddlib07__inv_1x inv_1x_54(.a(net_1636), .y(net_1496));
  muddlib07__inv_1x inv_1x_55(.a(net_1636), .y(net_1497));
  muddlib07__inv_1x inv_1x_56(.a(net_1636), .y(net_1498));
  muddlib07__inv_1x inv_1x_57(.a(net_1636), .y(net_1499));
  muddlib07__inv_1x inv_1x_58(.a(net_1636), .y(net_1500));
  muddlib07__inv_1x inv_1x_59(.a(net_1636), .y(net_1501));
  muddlib07__inv_1x inv_1x_60(.a(net_1636), .y(net_1502));
  muddlib07__inv_1x inv_1x_61(.a(net_1636), .y(net_1503));
  muddlib07__inv_1x inv_1x_62(.a(net_1636), .y(net_1504));
  muddlib07__inv_1x inv_1x_63(.a(net_1636), .y(net_1505));
  memsys_final__inv_16x inv_2x_0(.a(net_1095), .y(c4));
  memsys_final__inv_16x inv_2x_1(.a(net_1093), .y(c6));
  memsys_final__inv_16x inv_2x_2(.a(net_1091), .y(c5));
  memsys_final__inv_16x inv_2x_3(.a(net_1089), .y(c7));
  memsys_final__inv_16x inv_2x_4(.a(net_1087), .y(d4));
  memsys_final__inv_16x inv_2x_5(.a(net_1085), .y(d6));
  memsys_final__inv_16x inv_2x_6(.a(net_1634), .y(d3));
  memsys_final__inv_16x inv_2x_7(.a(net_761), .y(d7));
  memsys_final__inv_16x inv_2x_8(.a(net_759), .y(d5));
  memsys_final__inv_16x inv_2x_9(.a(net_758), .y(d1));
  muddlib07__inv_2x inv_2x_11(.a(net_1314), .y(net_1378));
  muddlib07__inv_2x inv_2x_12(.a(net_1315), .y(net_1379));
  muddlib07__inv_2x inv_2x_13(.a(net_1316), .y(net_1380));
  muddlib07__inv_2x inv_2x_14(.a(net_1317), .y(net_1381));
  muddlib07__inv_2x inv_2x_15(.a(net_1318), .y(net_1382));
  muddlib07__inv_2x inv_2x_16(.a(net_1319), .y(net_1383));
  muddlib07__inv_2x inv_2x_17(.a(net_1320), .y(net_1384));
  muddlib07__inv_2x inv_2x_18(.a(net_1321), .y(net_1385));
  muddlib07__inv_2x inv_2x_19(.a(net_1322), .y(net_1386));
  muddlib07__inv_2x inv_2x_20(.a(net_1323), .y(net_1387));
  muddlib07__inv_2x inv_2x_21(.a(net_1324), .y(net_1388));
  muddlib07__inv_2x inv_2x_22(.a(net_1325), .y(net_1389));
  muddlib07__inv_2x inv_2x_23(.a(net_1326), .y(net_1390));
  muddlib07__inv_2x inv_2x_24(.a(net_1327), .y(net_1391));
  muddlib07__inv_2x inv_2x_25(.a(net_1328), .y(net_1392));
  muddlib07__inv_2x inv_2x_26(.a(net_1329), .y(net_1393));
  muddlib07__inv_2x inv_2x_27(.a(net_1330), .y(net_1394));
  muddlib07__inv_2x inv_2x_28(.a(net_1331), .y(net_1395));
  muddlib07__inv_2x inv_2x_29(.a(net_1332), .y(net_1396));
  muddlib07__inv_2x inv_2x_30(.a(net_1333), .y(net_1397));
  muddlib07__inv_2x inv_2x_31(.a(net_1334), .y(net_1398));
  muddlib07__inv_2x inv_2x_32(.a(net_1335), .y(net_1399));
  muddlib07__inv_2x inv_2x_33(.a(net_1336), .y(net_1400));
  muddlib07__inv_2x inv_2x_34(.a(net_1337), .y(net_1401));
  muddlib07__inv_2x inv_2x_35(.a(net_1338), .y(net_1402));
  muddlib07__inv_2x inv_2x_36(.a(net_1339), .y(net_1403));
  muddlib07__inv_2x inv_2x_37(.a(net_1340), .y(net_1404));
  muddlib07__inv_2x inv_2x_38(.a(net_1341), .y(net_1405));
  muddlib07__inv_2x inv_2x_39(.a(net_1342), .y(net_1406));
  muddlib07__inv_2x inv_2x_40(.a(net_1343), .y(net_1407));
  muddlib07__inv_2x inv_2x_41(.a(net_1344), .y(net_1408));
  muddlib07__inv_2x inv_2x_42(.a(net_1345), .y(net_1409));
  muddlib07__inv_2x inv_2x_43(.a(net_1346), .y(net_1410));
  muddlib07__inv_2x inv_2x_44(.a(net_1347), .y(net_1411));
  muddlib07__inv_2x inv_2x_45(.a(net_1348), .y(net_1412));
  muddlib07__inv_2x inv_2x_46(.a(net_1349), .y(net_1413));
  muddlib07__inv_2x inv_2x_47(.a(net_1350), .y(net_1414));
  muddlib07__inv_2x inv_2x_48(.a(net_1351), .y(net_1415));
  muddlib07__inv_2x inv_2x_49(.a(net_1352), .y(net_1416));
  muddlib07__inv_2x inv_2x_50(.a(net_1353), .y(net_1417));
  muddlib07__inv_2x inv_2x_51(.a(net_1354), .y(net_1418));
  muddlib07__inv_2x inv_2x_52(.a(net_1355), .y(net_1419));
  muddlib07__inv_2x inv_2x_53(.a(net_1356), .y(net_1420));
  muddlib07__inv_2x inv_2x_54(.a(net_1357), .y(net_1421));
  muddlib07__inv_2x inv_2x_55(.a(net_1358), .y(net_1422));
  muddlib07__inv_2x inv_2x_56(.a(net_1359), .y(net_1423));
  muddlib07__inv_2x inv_2x_57(.a(net_1360), .y(net_1424));
  muddlib07__inv_2x inv_2x_58(.a(net_1361), .y(net_1425));
  muddlib07__inv_2x inv_2x_59(.a(net_1362), .y(net_1426));
  muddlib07__inv_2x inv_2x_60(.a(net_1363), .y(net_1427));
  muddlib07__inv_2x inv_2x_61(.a(net_1364), .y(net_1428));
  muddlib07__inv_2x inv_2x_62(.a(net_1365), .y(net_1429));
  muddlib07__inv_2x inv_2x_63(.a(net_1366), .y(net_1430));
  muddlib07__inv_2x inv_2x_64(.a(net_1367), .y(net_1431));
  muddlib07__inv_2x inv_2x_65(.a(net_1368), .y(net_1432));
  muddlib07__inv_2x inv_2x_66(.a(net_1369), .y(net_1433));
  muddlib07__inv_2x inv_2x_67(.a(net_1370), .y(net_1434));
  muddlib07__inv_2x inv_2x_68(.a(net_1371), .y(net_1435));
  muddlib07__inv_2x inv_2x_69(.a(net_1372), .y(net_1436));
  muddlib07__inv_2x inv_2x_70(.a(net_1373), .y(net_1437));
  muddlib07__inv_2x inv_2x_71(.a(net_1374), .y(net_1438));
  muddlib07__inv_2x inv_2x_72(.a(net_1375), .y(net_1439));
  muddlib07__inv_2x inv_2x_73(.a(net_1376), .y(net_1440));
  muddlib07__inv_2x inv_2x_74(.a(net_1377), .y(net_1441));
  memsys_final__inv_16x inv_3x_0(.a(net_1096), .y(c0));
  memsys_final__inv_16x inv_3x_1(.a(net_1094), .y(c2));
  memsys_final__inv_16x inv_3x_2(.a(net_1092), .y(c1));
  memsys_final__inv_16x inv_3x_3(.a(net_1090), .y(c3));
  memsys_final__inv_16x inv_3x_4(.a(net_1088), .y(d0));
  memsys_final__inv_16x inv_3x_5(.a(net_1086), .y(d2));
  memsys_final__inv_16x inv_16x_0(.a(net_1635), .y(net_1636));
  memsys_final__inv_16x inv_16x_1(.a(net_1570), .y(y[0]));
  memsys_final__inv_16x inv_16x_2(.a(net_1571), .y(y[1]));
  memsys_final__inv_16x inv_16x_3(.a(net_1572), .y(y[2]));
  memsys_final__inv_16x inv_16x_4(.a(net_1573), .y(y[3]));
  memsys_final__inv_16x inv_16x_5(.a(net_1574), .y(y[4]));
  memsys_final__inv_16x inv_16x_6(.a(net_1575), .y(y[5]));
  memsys_final__inv_16x inv_16x_7(.a(net_1576), .y(y[6]));
  memsys_final__inv_16x inv_16x_8(.a(net_1577), .y(y[7]));
  memsys_final__inv_16x inv_16x_9(.a(net_1578), .y(y[8]));
  memsys_final__inv_16x inv_16x_10(.a(net_1579), .y(y[9]));
  memsys_final__inv_16x inv_16x_11(.a(net_1580), .y(y[10]));
  memsys_final__inv_16x inv_16x_12(.a(net_1581), .y(y[11]));
  memsys_final__inv_16x inv_16x_13(.a(net_1582), .y(y[12]));
  memsys_final__inv_16x inv_16x_14(.a(net_1583), .y(y[13]));
  memsys_final__inv_16x inv_16x_15(.a(net_1584), .y(y[14]));
  memsys_final__inv_16x inv_16x_16(.a(net_1585), .y(y[15]));
  memsys_final__inv_16x inv_16x_17(.a(net_1586), .y(y[16]));
  memsys_final__inv_16x inv_16x_18(.a(net_1587), .y(y[17]));
  memsys_final__inv_16x inv_16x_19(.a(net_1588), .y(y[18]));
  memsys_final__inv_16x inv_16x_20(.a(net_1589), .y(y[19]));
  memsys_final__inv_16x inv_16x_21(.a(net_1590), .y(y[20]));
  memsys_final__inv_16x inv_16x_22(.a(net_1591), .y(y[21]));
  memsys_final__inv_16x inv_16x_23(.a(net_1592), .y(y[22]));
  memsys_final__inv_16x inv_16x_24(.a(net_1593), .y(y[23]));
  memsys_final__inv_16x inv_16x_25(.a(net_1594), .y(y[24]));
  memsys_final__inv_16x inv_16x_26(.a(net_1595), .y(y[25]));
  memsys_final__inv_16x inv_16x_27(.a(net_1596), .y(y[26]));
  memsys_final__inv_16x inv_16x_28(.a(net_1597), .y(y[27]));
  memsys_final__inv_16x inv_16x_29(.a(net_1598), .y(y[28]));
  memsys_final__inv_16x inv_16x_30(.a(net_1599), .y(y[29]));
  memsys_final__inv_16x inv_16x_31(.a(net_1600), .y(y[30]));
  memsys_final__inv_16x inv_16x_32(.a(net_1601), .y(y[31]));
  memsys_final__inv_16x inv_16x_33(.a(net_1602), .y(y[32]));
  memsys_final__inv_16x inv_16x_34(.a(net_1603), .y(y[33]));
  memsys_final__inv_16x inv_16x_35(.a(net_1604), .y(y[34]));
  memsys_final__inv_16x inv_16x_36(.a(net_1605), .y(y[35]));
  memsys_final__inv_16x inv_16x_37(.a(net_1606), .y(y[36]));
  memsys_final__inv_16x inv_16x_38(.a(net_1607), .y(y[37]));
  memsys_final__inv_16x inv_16x_39(.a(net_1608), .y(y[38]));
  memsys_final__inv_16x inv_16x_40(.a(net_1609), .y(y[39]));
  memsys_final__inv_16x inv_16x_41(.a(net_1610), .y(y[40]));
  memsys_final__inv_16x inv_16x_42(.a(net_1611), .y(y[41]));
  memsys_final__inv_16x inv_16x_43(.a(net_1612), .y(y[42]));
  memsys_final__inv_16x inv_16x_44(.a(net_1613), .y(y[43]));
  memsys_final__inv_16x inv_16x_45(.a(net_1614), .y(y[44]));
  memsys_final__inv_16x inv_16x_46(.a(net_1615), .y(y[45]));
  memsys_final__inv_16x inv_16x_47(.a(net_1616), .y(y[46]));
  memsys_final__inv_16x inv_16x_48(.a(net_1617), .y(y[47]));
  memsys_final__inv_16x inv_16x_49(.a(net_1618), .y(y[48]));
  memsys_final__inv_16x inv_16x_50(.a(net_1619), .y(y[49]));
  memsys_final__inv_16x inv_16x_51(.a(net_1620), .y(y[50]));
  memsys_final__inv_16x inv_16x_52(.a(net_1621), .y(y[51]));
  memsys_final__inv_16x inv_16x_53(.a(net_1622), .y(y[52]));
  memsys_final__inv_16x inv_16x_54(.a(net_1623), .y(y[53]));
  memsys_final__inv_16x inv_16x_55(.a(net_1624), .y(y[54]));
  memsys_final__inv_16x inv_16x_56(.a(net_1625), .y(y[55]));
  memsys_final__inv_16x inv_16x_57(.a(net_1626), .y(y[56]));
  memsys_final__inv_16x inv_16x_58(.a(net_1627), .y(y[57]));
  memsys_final__inv_16x inv_16x_59(.a(net_1628), .y(y[58]));
  memsys_final__inv_16x inv_16x_60(.a(net_1629), .y(y[59]));
  memsys_final__inv_16x inv_16x_61(.a(net_1630), .y(y[60]));
  memsys_final__inv_16x inv_16x_62(.a(net_1631), .y(y[61]));
  memsys_final__inv_16x inv_16x_63(.a(net_1632), .y(y[62]));
  memsys_final__inv_16x inv_16x_64(.a(net_1633), .y(y[63]));
  muddlib07__invbuf_4x invbuf_4_0(.s(a[0]), .s_out(a0buf), .sb_out(a0_b));
  muddlib07__invbuf_4x invbuf_4_1(.s(a[1]), .s_out(a1buf), .sb_out(a1_b));
  muddlib07__invbuf_4x invbuf_4_2(.s(a[3]), .s_out(a3buf), .sb_out(a3_b));
  muddlib07__invbuf_4x invbuf_4_3(.s(a[2]), .s_out(a2buf), .sb_out(a2_b));
  muddlib07__invbuf_4x invbuf_4_4(.s(a[5]), .s_out(a5buf), .sb_out(a5_b));
  muddlib07__invbuf_4x invbuf_4_5(.s(a[4]), .s_out(a4buf), .sb_out(a4_b));
  memsys_final__nand2_4x nand2_4x_0(.a(net_1378), .b(net_1442), .y(net_1633));
  memsys_final__nand2_4x nand2_4x_1(.a(net_1379), .b(net_1443), .y(net_1632));
  memsys_final__nand2_4x nand2_4x_2(.a(net_1380), .b(net_1444), .y(net_1631));
  memsys_final__nand2_4x nand2_4x_3(.a(net_1381), .b(net_1445), .y(net_1630));
  memsys_final__nand2_4x nand2_4x_4(.a(net_1382), .b(net_1446), .y(net_1629));
  memsys_final__nand2_4x nand2_4x_5(.a(net_1383), .b(net_1447), .y(net_1628));
  memsys_final__nand2_4x nand2_4x_6(.a(net_1384), .b(net_1448), .y(net_1627));
  memsys_final__nand2_4x nand2_4x_7(.a(net_1385), .b(net_1449), .y(net_1626));
  memsys_final__nand2_4x nand2_4x_8(.a(net_1386), .b(net_1450), .y(net_1625));
  memsys_final__nand2_4x nand2_4x_9(.a(net_1387), .b(net_1451), .y(net_1624));
  memsys_final__nand2_4x nand2_4x_10(.a(net_1388), .b(net_1452), 
      .y(net_1623));
  memsys_final__nand2_4x nand2_4x_11(.a(net_1389), .b(net_1453), 
      .y(net_1622));
  memsys_final__nand2_4x nand2_4x_12(.a(net_1390), .b(net_1454), 
      .y(net_1621));
  memsys_final__nand2_4x nand2_4x_13(.a(net_1391), .b(net_1455), 
      .y(net_1620));
  memsys_final__nand2_4x nand2_4x_14(.a(net_1392), .b(net_1456), 
      .y(net_1619));
  memsys_final__nand2_4x nand2_4x_15(.a(net_1393), .b(net_1457), 
      .y(net_1618));
  memsys_final__nand2_4x nand2_4x_16(.a(net_1394), .b(net_1458), 
      .y(net_1617));
  memsys_final__nand2_4x nand2_4x_17(.a(net_1395), .b(net_1459), 
      .y(net_1616));
  memsys_final__nand2_4x nand2_4x_18(.a(net_1396), .b(net_1460), 
      .y(net_1615));
  memsys_final__nand2_4x nand2_4x_19(.a(net_1397), .b(net_1461), 
      .y(net_1614));
  memsys_final__nand2_4x nand2_4x_20(.a(net_1398), .b(net_1462), 
      .y(net_1613));
  memsys_final__nand2_4x nand2_4x_21(.a(net_1399), .b(net_1463), 
      .y(net_1612));
  memsys_final__nand2_4x nand2_4x_22(.a(net_1400), .b(net_1464), 
      .y(net_1611));
  memsys_final__nand2_4x nand2_4x_23(.a(net_1401), .b(net_1465), 
      .y(net_1610));
  memsys_final__nand2_4x nand2_4x_24(.a(net_1402), .b(net_1466), 
      .y(net_1609));
  memsys_final__nand2_4x nand2_4x_25(.a(net_1403), .b(net_1467), 
      .y(net_1608));
  memsys_final__nand2_4x nand2_4x_26(.a(net_1404), .b(net_1468), 
      .y(net_1607));
  memsys_final__nand2_4x nand2_4x_27(.a(net_1405), .b(net_1469), 
      .y(net_1606));
  memsys_final__nand2_4x nand2_4x_28(.a(net_1406), .b(net_1470), 
      .y(net_1605));
  memsys_final__nand2_4x nand2_4x_29(.a(net_1407), .b(net_1471), 
      .y(net_1604));
  memsys_final__nand2_4x nand2_4x_30(.a(net_1408), .b(net_1472), 
      .y(net_1603));
  memsys_final__nand2_4x nand2_4x_31(.a(net_1409), .b(net_1473), 
      .y(net_1602));
  memsys_final__nand2_4x nand2_4x_32(.a(net_1410), .b(net_1474), 
      .y(net_1601));
  memsys_final__nand2_4x nand2_4x_33(.a(net_1411), .b(net_1475), 
      .y(net_1600));
  memsys_final__nand2_4x nand2_4x_34(.a(net_1412), .b(net_1476), 
      .y(net_1599));
  memsys_final__nand2_4x nand2_4x_35(.a(net_1413), .b(net_1477), 
      .y(net_1598));
  memsys_final__nand2_4x nand2_4x_36(.a(net_1414), .b(net_1478), 
      .y(net_1597));
  memsys_final__nand2_4x nand2_4x_37(.a(net_1415), .b(net_1479), 
      .y(net_1596));
  memsys_final__nand2_4x nand2_4x_38(.a(net_1416), .b(net_1480), 
      .y(net_1595));
  memsys_final__nand2_4x nand2_4x_39(.a(net_1417), .b(net_1481), 
      .y(net_1594));
  memsys_final__nand2_4x nand2_4x_40(.a(net_1418), .b(net_1482), 
      .y(net_1593));
  memsys_final__nand2_4x nand2_4x_41(.a(net_1419), .b(net_1483), 
      .y(net_1592));
  memsys_final__nand2_4x nand2_4x_42(.a(net_1420), .b(net_1484), 
      .y(net_1591));
  memsys_final__nand2_4x nand2_4x_43(.a(net_1421), .b(net_1485), 
      .y(net_1590));
  memsys_final__nand2_4x nand2_4x_44(.a(net_1422), .b(net_1486), 
      .y(net_1589));
  memsys_final__nand2_4x nand2_4x_45(.a(net_1423), .b(net_1487), 
      .y(net_1588));
  memsys_final__nand2_4x nand2_4x_46(.a(net_1424), .b(net_1488), 
      .y(net_1587));
  memsys_final__nand2_4x nand2_4x_47(.a(net_1425), .b(net_1489), 
      .y(net_1586));
  memsys_final__nand2_4x nand2_4x_48(.a(net_1426), .b(net_1490), 
      .y(net_1585));
  memsys_final__nand2_4x nand2_4x_49(.a(net_1427), .b(net_1491), 
      .y(net_1584));
  memsys_final__nand2_4x nand2_4x_50(.a(net_1428), .b(net_1492), 
      .y(net_1583));
  memsys_final__nand2_4x nand2_4x_51(.a(net_1429), .b(net_1493), 
      .y(net_1582));
  memsys_final__nand2_4x nand2_4x_52(.a(net_1430), .b(net_1494), 
      .y(net_1581));
  memsys_final__nand2_4x nand2_4x_53(.a(net_1431), .b(net_1495), 
      .y(net_1580));
  memsys_final__nand2_4x nand2_4x_54(.a(net_1432), .b(net_1496), 
      .y(net_1579));
  memsys_final__nand2_4x nand2_4x_55(.a(net_1433), .b(net_1497), 
      .y(net_1578));
  memsys_final__nand2_4x nand2_4x_56(.a(net_1434), .b(net_1498), 
      .y(net_1577));
  memsys_final__nand2_4x nand2_4x_57(.a(net_1435), .b(net_1499), 
      .y(net_1576));
  memsys_final__nand2_4x nand2_4x_58(.a(net_1436), .b(net_1500), 
      .y(net_1575));
  memsys_final__nand2_4x nand2_4x_59(.a(net_1437), .b(net_1501), 
      .y(net_1574));
  memsys_final__nand2_4x nand2_4x_60(.a(net_1438), .b(net_1502), 
      .y(net_1573));
  memsys_final__nand2_4x nand2_4x_61(.a(net_1439), .b(net_1503), 
      .y(net_1572));
  memsys_final__nand2_4x nand2_4x_62(.a(net_1440), .b(net_1504), 
      .y(net_1571));
  memsys_final__nand2_4x nand2_4x_63(.a(net_1441), .b(net_1505), 
      .y(net_1570));
  memsys_final__nand3_2x nand2_xx_0(.a(a0buf), .b(a1_b), .c(a2buf), 
      .y(net_1091));
  memsys_final__nand3_2x nand2_xx_1(.a(a3_b), .b(a4buf), .c(a5buf), 
      .y(net_1085));
  memsys_final__nand3_2x nand2_xx_2(.a(a0buf), .b(a1_b), .c(a2_b), 
      .y(net_1092));
  memsys_final__nand3_2x nand2_xx_3(.a(a3_b), .b(a4buf), .c(a5_b), 
      .y(net_1086));
  memsys_final__nand3_2x nand2_xx_4(.a(a0_b), .b(a1buf), .c(a2buf), 
      .y(net_1093));
  memsys_final__nand3_2x nand2_xx_5(.a(a3_b), .b(a4_b), .c(a5buf), 
      .y(net_1087));
  memsys_final__nand3_2x nand2_xx_6(.a(a0_b), .b(a1buf), .c(a2_b), 
      .y(net_1094));
  memsys_final__nand3_2x nand2_xx_7(.a(a3_b), .b(a4_b), .c(a5_b), 
      .y(net_1088));
  memsys_final__nand3_2x nand2_xx_8(.a(a0_b), .b(a1_b), .c(a2buf), 
      .y(net_1095));
  memsys_final__nand3_2x nand2_xx_9(.a(a0buf), .b(a1buf), .c(a2buf), 
      .y(net_1089));
  memsys_final__nand3_2x nand2_xx_10(.a(a0_b), .b(a1_b), .c(a2_b), 
      .y(net_1096));
  memsys_final__nand3_2x nand2_xx_11(.a(a0buf), .b(a1buf), .c(a2_b), 
      .y(net_1090));
  muddlib07__nand2_1x nand2_xx_12(.a(d7), .b(c7), .y(net_1314));
  memsys_final__nand3_2x nand3_2x_12(.a(a3buf), .b(a4_b), .c(a5_b), 
      .y(net_758));
  memsys_final__nand3_2x nand3_2x_13(.a(a3buf), .b(a4_b), .c(a5buf), 
      .y(net_759));
  memsys_final__nand3_2x nand3_2x_14(.a(a3buf), .b(a4buf), .c(a5_b), 
      .y(net_1634));
  memsys_final__nand3_2x nand3_2x_15(.a(a3buf), .b(a4buf), .c(a5buf), 
      .y(net_761));
  muddlib07__nand2_1x nand3_45_63(.a(d0), .b(c0), .y(net_1377));
  muddlib07__nand2_1x nand3_45_64(.a(d0), .b(c1), .y(net_1376));
  muddlib07__nand2_1x nand3_45_65(.a(d0), .b(c2), .y(net_1375));
  muddlib07__nand2_1x nand3_45_66(.a(d0), .b(c3), .y(net_1374));
  muddlib07__nand2_1x nand3_45_67(.a(d0), .b(c4), .y(net_1373));
  muddlib07__nand2_1x nand3_45_68(.a(d0), .b(c5), .y(net_1372));
  muddlib07__nand2_1x nand3_45_69(.a(d0), .b(c6), .y(net_1371));
  muddlib07__nand2_1x nand3_45_70(.a(d0), .b(c7), .y(net_1370));
  muddlib07__nand2_1x nand3_45_71(.a(d1), .b(c0), .y(net_1369));
  muddlib07__nand2_1x nand3_45_72(.a(d1), .b(c1), .y(net_1368));
  muddlib07__nand2_1x nand3_45_73(.a(d1), .b(c2), .y(net_1367));
  muddlib07__nand2_1x nand3_45_74(.a(d1), .b(c3), .y(net_1366));
  muddlib07__nand2_1x nand3_45_75(.a(d1), .b(c4), .y(net_1365));
  muddlib07__nand2_1x nand3_45_76(.a(d1), .b(c5), .y(net_1364));
  muddlib07__nand2_1x nand3_45_77(.a(d1), .b(c6), .y(net_1363));
  muddlib07__nand2_1x nand3_45_78(.a(d1), .b(c7), .y(net_1362));
  muddlib07__nand2_1x nand3_45_79(.a(d2), .b(c0), .y(net_1361));
  muddlib07__nand2_1x nand3_45_80(.a(d2), .b(c1), .y(net_1360));
  muddlib07__nand2_1x nand3_45_81(.a(d2), .b(c2), .y(net_1359));
  muddlib07__nand2_1x nand3_45_82(.a(d2), .b(c3), .y(net_1358));
  muddlib07__nand2_1x nand3_45_83(.a(d2), .b(c4), .y(net_1357));
  muddlib07__nand2_1x nand3_45_84(.a(d2), .b(c5), .y(net_1356));
  muddlib07__nand2_1x nand3_45_85(.a(d2), .b(c6), .y(net_1355));
  muddlib07__nand2_1x nand3_45_86(.a(d2), .b(c7), .y(net_1354));
  muddlib07__nand2_1x nand3_45_87(.a(d3), .b(c0), .y(net_1353));
  muddlib07__nand2_1x nand3_45_88(.a(d3), .b(c1), .y(net_1352));
  muddlib07__nand2_1x nand3_45_89(.a(d3), .b(c2), .y(net_1351));
  muddlib07__nand2_1x nand3_45_90(.a(d3), .b(c3), .y(net_1350));
  muddlib07__nand2_1x nand3_45_91(.a(d3), .b(c4), .y(net_1349));
  muddlib07__nand2_1x nand3_45_92(.a(d3), .b(c5), .y(net_1348));
  muddlib07__nand2_1x nand3_45_93(.a(d3), .b(c6), .y(net_1347));
  muddlib07__nand2_1x nand3_45_94(.a(d3), .b(c7), .y(net_1346));
  muddlib07__nand2_1x nand3_45_95(.a(d4), .b(c0), .y(net_1345));
  muddlib07__nand2_1x nand3_45_96(.a(d4), .b(c1), .y(net_1344));
  muddlib07__nand2_1x nand3_45_97(.a(d4), .b(c2), .y(net_1343));
  muddlib07__nand2_1x nand3_45_98(.a(d4), .b(c3), .y(net_1342));
  muddlib07__nand2_1x nand3_45_99(.a(d4), .b(c4), .y(net_1341));
  muddlib07__nand2_1x nand3_45_100(.a(d4), .b(c5), .y(net_1340));
  muddlib07__nand2_1x nand3_45_101(.a(d4), .b(c6), .y(net_1339));
  muddlib07__nand2_1x nand3_45_102(.a(d4), .b(c7), .y(net_1338));
  muddlib07__nand2_1x nand3_45_103(.a(d5), .b(c0), .y(net_1337));
  muddlib07__nand2_1x nand3_45_104(.a(d5), .b(c1), .y(net_1336));
  muddlib07__nand2_1x nand3_45_105(.a(d5), .b(c2), .y(net_1335));
  muddlib07__nand2_1x nand3_45_106(.a(d5), .b(c3), .y(net_1334));
  muddlib07__nand2_1x nand3_45_107(.a(d5), .b(c4), .y(net_1333));
  muddlib07__nand2_1x nand3_45_108(.a(d5), .b(c5), .y(net_1332));
  muddlib07__nand2_1x nand3_45_109(.a(d5), .b(c6), .y(net_1331));
  muddlib07__nand2_1x nand3_45_110(.a(d5), .b(c7), .y(net_1330));
  muddlib07__nand2_1x nand3_45_111(.a(d6), .b(c0), .y(net_1329));
  muddlib07__nand2_1x nand3_45_112(.a(d6), .b(c1), .y(net_1328));
  muddlib07__nand2_1x nand3_45_113(.a(d6), .b(c2), .y(net_1327));
  muddlib07__nand2_1x nand3_45_114(.a(d6), .b(c3), .y(net_1326));
  muddlib07__nand2_1x nand3_45_115(.a(d6), .b(c4), .y(net_1325));
  muddlib07__nand2_1x nand3_45_116(.a(d6), .b(c5), .y(net_1324));
  muddlib07__nand2_1x nand3_45_117(.a(d6), .b(c6), .y(net_1323));
  muddlib07__nand2_1x nand3_45_118(.a(d6), .b(c7), .y(net_1322));
  muddlib07__nand2_1x nand3_45_119(.a(d7), .b(c0), .y(net_1321));
  muddlib07__nand2_1x nand3_45_120(.a(d7), .b(c1), .y(net_1320));
  muddlib07__nand2_1x nand3_45_121(.a(d7), .b(c2), .y(net_1319));
  muddlib07__nand2_1x nand3_45_122(.a(d7), .b(c3), .y(net_1318));
  muddlib07__nand2_1x nand3_45_123(.a(d7), .b(c4), .y(net_1317));
  muddlib07__nand2_1x nand3_45_124(.a(d7), .b(c5), .y(net_1316));
  muddlib07__nand2_1x nand3_45_125(.a(d7), .b(c6), .y(net_1315));
  muddlib07__invbuf_4x ph1(.s(ph2), .s_out(net_1635), .sb_out(ph1_sb_out));
endmodule   /* memsys_final__decoder64b */

module memsys_final__cacheram(adr, din, ph1, ph2, rwb, dout);
  input [6:0] adr;
  input [52:0] din;
  input ph1;
  input ph2;
  input rwb;
  output [52:0] dout;

  supply1 vdd;
  supply0 gnd;
  wire adr6_b_buff, adr6_buff, ph1_b, ph1_b_buff, ph2_b_buff, rwb_buff;
  wire [63:0] word_buff;

  memsys_final__cache_buffers cache_bu_2(.adr(adr[6]), .ph1(ph1), .ph2(ph2), 
      .rwb(rwb), .word(word_buff[63:0]), .adr_b(adr6_b_buff), 
      .adr_buff(adr6_buff), .ph1_b(ph1_b), .ph1_bc_b(ph1_b_buff), 
      .ph2_b(ph2_b_buff), .rwb_buff(rwb_buff));
  memsys_final__cacheramarray cacheram_4(.adr(adr6_buff), .adr_b(adr6_b_buff), 
      .din(din[52:0]), .ph1_b(ph1_b), .ph1_b_buff(ph1_b_buff), 
      .ph2_b(ph2_b_buff), .rwb(rwb_buff), .word(word_buff[63:0]), 
      .dout(dout[52:0]));
  memsys_final__decoder64b decoder6_8(.a(adr[5:0]), .ph2(ph2), 
      .y(word_buff[63:0]));
endmodule   /* memsys_final__cacheram */

module muddlib07__mux2_dp_1x(d0, d1, s, sb, y);
  input d0;
  input d1;
  input s;
  input sb;
  output y;

  supply1 vdd;
  supply0 gnd;
  wire net_12, net_15, net_3, net_4, net_8;

  tranif1 nmos_0(gnd, net_3, d1);
  tranif1 nmos_1(gnd, net_4, d0);
  tranif1 nmos_2(net_3, net_8, s);
  tranif1 nmos_3(net_4, net_8, sb);
  tranif1 nmos_4(gnd, y, net_8);
  tranif0 pmos_0(net_8, net_15, sb);
  tranif0 pmos_1(net_15, vdd, d1);
  tranif0 pmos_2(net_8, net_12, s);
  tranif0 pmos_3(net_12, vdd, d0);
  tranif0 pmos_4(y, vdd, net_8);
endmodule   /* muddlib07__mux2_dp_1x */

module memsys_final__mux2_zip(s, s_out, sb_out);
  input s;
  output s_out;
  output sb_out;

  supply1 vdd;
  supply0 gnd;
  muddlib07__inv_4x inv_4x_3(.a(s), .y(sb_out));
  muddlib07__inv_4x inv_4x_4(.a(sb_out), .y(s_out));
endmodule   /* memsys_final__mux2_zip */

module memsys_final__mux2_1x_32(d0, d1, s, y);
  input [31:0] d0;
  input [31:0] d1;
  input s;
  output [31:0] y;

  supply1 vdd;
  supply0 gnd;
  wire sb, sbb;

  muddlib07__mux2_dp_1x mux2_dp_1x_31_(.d0(d0[31]), .d1(d1[31]), .s(sbb), 
      .sb(sb), .y(y[31]));
  muddlib07__mux2_dp_1x mux2_dp_1x_30_(.d0(d0[30]), .d1(d1[30]), .s(sbb), 
      .sb(sb), .y(y[30]));
  muddlib07__mux2_dp_1x mux2_dp_1x_29_(.d0(d0[29]), .d1(d1[29]), .s(sbb), 
      .sb(sb), .y(y[29]));
  muddlib07__mux2_dp_1x mux2_dp_1x_28_(.d0(d0[28]), .d1(d1[28]), .s(sbb), 
      .sb(sb), .y(y[28]));
  muddlib07__mux2_dp_1x mux2_dp_1x_27_(.d0(d0[27]), .d1(d1[27]), .s(sbb), 
      .sb(sb), .y(y[27]));
  muddlib07__mux2_dp_1x mux2_dp_1x_26_(.d0(d0[26]), .d1(d1[26]), .s(sbb), 
      .sb(sb), .y(y[26]));
  muddlib07__mux2_dp_1x mux2_dp_1x_25_(.d0(d0[25]), .d1(d1[25]), .s(sbb), 
      .sb(sb), .y(y[25]));
  muddlib07__mux2_dp_1x mux2_dp_1x_24_(.d0(d0[24]), .d1(d1[24]), .s(sbb), 
      .sb(sb), .y(y[24]));
  muddlib07__mux2_dp_1x mux2_dp_1x_23_(.d0(d0[23]), .d1(d1[23]), .s(sbb), 
      .sb(sb), .y(y[23]));
  muddlib07__mux2_dp_1x mux2_dp_1x_22_(.d0(d0[22]), .d1(d1[22]), .s(sbb), 
      .sb(sb), .y(y[22]));
  muddlib07__mux2_dp_1x mux2_dp_1x_21_(.d0(d0[21]), .d1(d1[21]), .s(sbb), 
      .sb(sb), .y(y[21]));
  muddlib07__mux2_dp_1x mux2_dp_1x_20_(.d0(d0[20]), .d1(d1[20]), .s(sbb), 
      .sb(sb), .y(y[20]));
  muddlib07__mux2_dp_1x mux2_dp_1x_19_(.d0(d0[19]), .d1(d1[19]), .s(sbb), 
      .sb(sb), .y(y[19]));
  muddlib07__mux2_dp_1x mux2_dp_1x_18_(.d0(d0[18]), .d1(d1[18]), .s(sbb), 
      .sb(sb), .y(y[18]));
  muddlib07__mux2_dp_1x mux2_dp_1x_17_(.d0(d0[17]), .d1(d1[17]), .s(sbb), 
      .sb(sb), .y(y[17]));
  muddlib07__mux2_dp_1x mux2_dp_1x_16_(.d0(d0[16]), .d1(d1[16]), .s(sbb), 
      .sb(sb), .y(y[16]));
  muddlib07__mux2_dp_1x mux2_dp_1x_15_(.d0(d0[15]), .d1(d1[15]), .s(sbb), 
      .sb(sb), .y(y[15]));
  muddlib07__mux2_dp_1x mux2_dp_1x_14_(.d0(d0[14]), .d1(d1[14]), .s(sbb), 
      .sb(sb), .y(y[14]));
  muddlib07__mux2_dp_1x mux2_dp_1x_13_(.d0(d0[13]), .d1(d1[13]), .s(sbb), 
      .sb(sb), .y(y[13]));
  muddlib07__mux2_dp_1x mux2_dp_1x_12_(.d0(d0[12]), .d1(d1[12]), .s(sbb), 
      .sb(sb), .y(y[12]));
  muddlib07__mux2_dp_1x mux2_dp_1x_11_(.d0(d0[11]), .d1(d1[11]), .s(sbb), 
      .sb(sb), .y(y[11]));
  muddlib07__mux2_dp_1x mux2_dp_1x_10_(.d0(d0[10]), .d1(d1[10]), .s(sbb), 
      .sb(sb), .y(y[10]));
  muddlib07__mux2_dp_1x mux2_dp_1x_9_(.d0(d0[9]), .d1(d1[9]), .s(sbb), .sb(sb), 
      .y(y[9]));
  muddlib07__mux2_dp_1x mux2_dp_1x_8_(.d0(d0[8]), .d1(d1[8]), .s(sbb), .sb(sb), 
      .y(y[8]));
  muddlib07__mux2_dp_1x mux2_dp_1x_7_(.d0(d0[7]), .d1(d1[7]), .s(sbb), .sb(sb), 
      .y(y[7]));
  muddlib07__mux2_dp_1x mux2_dp_1x_6_(.d0(d0[6]), .d1(d1[6]), .s(sbb), .sb(sb), 
      .y(y[6]));
  muddlib07__mux2_dp_1x mux2_dp_1x_5_(.d0(d0[5]), .d1(d1[5]), .s(sbb), .sb(sb), 
      .y(y[5]));
  muddlib07__mux2_dp_1x mux2_dp_1x_4_(.d0(d0[4]), .d1(d1[4]), .s(sbb), .sb(sb), 
      .y(y[4]));
  muddlib07__mux2_dp_1x mux2_dp_1x_3_(.d0(d0[3]), .d1(d1[3]), .s(sbb), .sb(sb), 
      .y(y[3]));
  muddlib07__mux2_dp_1x mux2_dp_1x_2_(.d0(d0[2]), .d1(d1[2]), .s(sbb), .sb(sb), 
      .y(y[2]));
  muddlib07__mux2_dp_1x mux2_dp_1x_1_(.d0(d0[1]), .d1(d1[1]), .s(sbb), .sb(sb), 
      .y(y[1]));
  muddlib07__mux2_dp_1x mux2_dp_1x_0_(.d0(d0[0]), .d1(d1[0]), .s(sbb), .sb(sb), 
      .y(y[0]));
  memsys_final__mux2_zip mux2_zip_1(.s(s), .s_out(sbb), .sb_out(sb));
endmodule   /* memsys_final__mux2_1x_32 */

module memsys_final__tribuf_32(d, en, y);
  input [31:0] d;
  input en;
  output [31:0] y;

  supply1 vdd;
  supply0 gnd;
  wire net_8, net_9;

  memsys_final__buftri_zip buftri_z_0(.en(en), .en_out(net_8), 
      .enb_out(net_9));
  muddlib07__buftri_dp_1x tribuf_31_(.d(d[31]), .en(net_8), .enb(net_9), 
      .y(y[31]));
  muddlib07__buftri_dp_1x tribuf_30_(.d(d[30]), .en(net_8), .enb(net_9), 
      .y(y[30]));
  muddlib07__buftri_dp_1x tribuf_29_(.d(d[29]), .en(net_8), .enb(net_9), 
      .y(y[29]));
  muddlib07__buftri_dp_1x tribuf_28_(.d(d[28]), .en(net_8), .enb(net_9), 
      .y(y[28]));
  muddlib07__buftri_dp_1x tribuf_27_(.d(d[27]), .en(net_8), .enb(net_9), 
      .y(y[27]));
  muddlib07__buftri_dp_1x tribuf_26_(.d(d[26]), .en(net_8), .enb(net_9), 
      .y(y[26]));
  muddlib07__buftri_dp_1x tribuf_25_(.d(d[25]), .en(net_8), .enb(net_9), 
      .y(y[25]));
  muddlib07__buftri_dp_1x tribuf_24_(.d(d[24]), .en(net_8), .enb(net_9), 
      .y(y[24]));
  muddlib07__buftri_dp_1x tribuf_23_(.d(d[23]), .en(net_8), .enb(net_9), 
      .y(y[23]));
  muddlib07__buftri_dp_1x tribuf_22_(.d(d[22]), .en(net_8), .enb(net_9), 
      .y(y[22]));
  muddlib07__buftri_dp_1x tribuf_21_(.d(d[21]), .en(net_8), .enb(net_9), 
      .y(y[21]));
  muddlib07__buftri_dp_1x tribuf_20_(.d(d[20]), .en(net_8), .enb(net_9), 
      .y(y[20]));
  muddlib07__buftri_dp_1x tribuf_19_(.d(d[19]), .en(net_8), .enb(net_9), 
      .y(y[19]));
  muddlib07__buftri_dp_1x tribuf_18_(.d(d[18]), .en(net_8), .enb(net_9), 
      .y(y[18]));
  muddlib07__buftri_dp_1x tribuf_17_(.d(d[17]), .en(net_8), .enb(net_9), 
      .y(y[17]));
  muddlib07__buftri_dp_1x tribuf_16_(.d(d[16]), .en(net_8), .enb(net_9), 
      .y(y[16]));
  muddlib07__buftri_dp_1x tribuf_15_(.d(d[15]), .en(net_8), .enb(net_9), 
      .y(y[15]));
  muddlib07__buftri_dp_1x tribuf_14_(.d(d[14]), .en(net_8), .enb(net_9), 
      .y(y[14]));
  muddlib07__buftri_dp_1x tribuf_13_(.d(d[13]), .en(net_8), .enb(net_9), 
      .y(y[13]));
  muddlib07__buftri_dp_1x tribuf_12_(.d(d[12]), .en(net_8), .enb(net_9), 
      .y(y[12]));
  muddlib07__buftri_dp_1x tribuf_11_(.d(d[11]), .en(net_8), .enb(net_9), 
      .y(y[11]));
  muddlib07__buftri_dp_1x tribuf_10_(.d(d[10]), .en(net_8), .enb(net_9), 
      .y(y[10]));
  muddlib07__buftri_dp_1x tribuf_9_(.d(d[9]), .en(net_8), .enb(net_9), 
      .y(y[9]));
  muddlib07__buftri_dp_1x tribuf_8_(.d(d[8]), .en(net_8), .enb(net_9), 
      .y(y[8]));
  muddlib07__buftri_dp_1x tribuf_7_(.d(d[7]), .en(net_8), .enb(net_9), 
      .y(y[7]));
  muddlib07__buftri_dp_1x tribuf_6_(.d(d[6]), .en(net_8), .enb(net_9), 
      .y(y[6]));
  muddlib07__buftri_dp_1x tribuf_5_(.d(d[5]), .en(net_8), .enb(net_9), 
      .y(y[5]));
  muddlib07__buftri_dp_1x tribuf_4_(.d(d[4]), .en(net_8), .enb(net_9), 
      .y(y[4]));
  muddlib07__buftri_dp_1x tribuf_3_(.d(d[3]), .en(net_8), .enb(net_9), 
      .y(y[3]));
  muddlib07__buftri_dp_1x tribuf_2_(.d(d[2]), .en(net_8), .enb(net_9), 
      .y(y[2]));
  muddlib07__buftri_dp_1x tribuf_1_(.d(d[1]), .en(net_8), .enb(net_9), 
      .y(y[1]));
  muddlib07__buftri_dp_1x tribuf_0_(.d(d[0]), .en(net_8), .enb(net_9), 
      .y(y[0]));
endmodule   /* memsys_final__tribuf_32 */

module memsys_final__dataout(cacheline, rwb, waiting, data, memdata);
  input [31:0] cacheline;
  input rwb;
  input waiting;
  input [31:0] data;
  input [31:0] memdata;

  supply1 vdd;
  supply0 gnd;
  wire rwb_b;
  wire [31:0] readdata;

  muddlib07__inv_1x inv_1x_0(.a(rwb), .y(rwb_b));
  memsys_final__mux2_1x_32 mux2_1x__0(.d0(cacheline[31:0]), .d1(memdata[31:0]), 
      .s(waiting), .y(readdata[31:0]));
  memsys_final__tribuf_32 tribuf_3_0(.d(readdata[31:0]), .en(rwb), 
      .y(data[31:0]));
  memsys_final__tribuf_32 tribuf_3_1(.d(data[31:0]), .en(rwb_b), 
      .y(memdata[31:0]));
endmodule   /* memsys_final__dataout */

module memsys_final__mux2_1x_4(d0, d1, s, y);
  input [3:0] d0;
  input [3:0] d1;
  input s;
  output [3:0] y;

  supply1 vdd;
  supply0 gnd;
  wire net_17, net_18;

  muddlib07__mux2_dp_1x mux2_dp_3_(.d0(d0[3]), .d1(d1[3]), .s(net_17), 
      .sb(net_18), .y(y[3]));
  muddlib07__mux2_dp_1x mux2_dp_2_(.d0(d0[2]), .d1(d1[2]), .s(net_17), 
      .sb(net_18), .y(y[2]));
  muddlib07__mux2_dp_1x mux2_dp_1_(.d0(d0[1]), .d1(d1[1]), .s(net_17), 
      .sb(net_18), .y(y[1]));
  muddlib07__mux2_dp_1x mux2_dp_0_(.d0(d0[0]), .d1(d1[0]), .s(net_17), 
      .sb(net_18), .y(y[0]));
  memsys_final__mux2_zip mux2_zip_0(.s(s), .s_out(net_17), .sb_out(net_18));
endmodule   /* memsys_final__mux2_1x_4 */

module memsys_final__dcache(adr, adr_1, byteen, en, memdone, ph1, ph2, reset, 
      rwb, done, membyteen, memen, data, memdata);
  input [27:0] adr;
  input [29:29] adr_1;
  input [3:0] byteen;
  input en;
  input memdone;
  input ph1;
  input ph2;
  input reset;
  input rwb;
  output done;
  output [3:0] membyteen;
  output memen;
  input [31:0] data;
  input [31:0] memdata;

  supply1 vdd;
  supply0 gnd;
  wire bypass, cacheramrwb, reading, valid, validnew, waiting_b;
  wire [31:0] cacheline;
  wire [31:0] cachelinenew;
  wire [19:0] tagdata;

  memsys_final__byteenlog byteenlo_0(.byteen(byteen[3:0]), .memdone(memdone), 
      .reading(reading), .validnew(validnew));
  memsys_final__cachecontroller cachecon_2(.adr(adr[27:7]), 
      .adr_1(adr_1[29:29]), .en(en), .memdone(memdone), .reset(reset), 
      .rwb(rwb), .tagdata(tagdata[19:0]), .valid(valid), .bypass(bypass), 
      .done(done), .reading(reading), .waiting(memen), .ph1(ph1), .ph2(ph2));
  memsys_final__cacheram cacheram_1(.adr(adr[6:0]), .din({cachelinenew[31], 
      cachelinenew[30], cachelinenew[29], cachelinenew[28], cachelinenew[27], 
      adr[26], cachelinenew[26], adr[25], cachelinenew[25], adr[24], 
      cachelinenew[24], adr[23], cachelinenew[23], adr[22], cachelinenew[22], 
      adr[21], cachelinenew[21], adr[20], cachelinenew[20], adr[19], 
      cachelinenew[19], adr[18], cachelinenew[18], adr[17], cachelinenew[17], 
      adr[16], cachelinenew[16], adr[15], cachelinenew[15], adr[14], 
      cachelinenew[14], adr[13], cachelinenew[13], adr[12], cachelinenew[12], 
      adr[11], cachelinenew[11], adr[10], cachelinenew[10], adr[9], 
      cachelinenew[9], adr[8], cachelinenew[8], adr[7], cachelinenew[7], 
      cachelinenew[6], cachelinenew[5], cachelinenew[4], cachelinenew[3], 
      cachelinenew[2], validnew, cachelinenew[1], cachelinenew[0]}), .ph1(ph1), 
      .ph2(ph2), .rwb(cacheramrwb), .dout({cacheline[31], cacheline[30], 
      cacheline[29], cacheline[28], cacheline[27], tagdata[19], cacheline[26], 
      tagdata[18], cacheline[25], tagdata[17], cacheline[24], tagdata[16], 
      cacheline[23], tagdata[15], cacheline[22], tagdata[14], cacheline[21], 
      tagdata[13], cacheline[20], tagdata[12], cacheline[19], tagdata[11], 
      cacheline[18], tagdata[10], cacheline[17], tagdata[9], cacheline[16], 
      tagdata[8], cacheline[15], tagdata[7], cacheline[14], tagdata[6], 
      cacheline[13], tagdata[5], cacheline[12], tagdata[4], cacheline[11], 
      tagdata[3], cacheline[10], tagdata[2], cacheline[9], tagdata[1], 
      cacheline[8], tagdata[0], cacheline[7], cacheline[6], cacheline[5], 
      cacheline[4], cacheline[3], cacheline[2], valid, cacheline[1], 
      cacheline[0]}));
  memsys_final__dataout dataout_1(.cacheline(cacheline[31:0]), .rwb(rwb), 
      .waiting(memen), .data(data[31:0]), .memdata(memdata[31:0]));
  muddlib07__inv_1x inv_1x_0(.a(memen), .y(waiting_b));
  memsys_final__mux2_1x_32 mux2_1x__2(.d0(data[31:0]), .d1(memdata[31:0]), 
      .s(reading), .y(cachelinenew[31:0]));
  memsys_final__mux2_1x_4 mux2_4_0(.d0(byteen[3:0]), .d1({vdd, vdd, vdd, vdd}), 
      .s(reading), .y(membyteen[3:0]));
  muddlib07__or2_1x or2_1x_0(.a(bypass), .b(waiting_b), .y(cacheramrwb));
endmodule   /* memsys_final__dcache */

module memsys_final__greenblock(imembyteen, imemen, ion, memdone, swc_imemrwbb, 
      wbdone, imemdone, wbbyteen, wben);
  input [3:0] imembyteen;
  input imemen;
  input ion;
  input memdone;
  input swc_imemrwbb;
  input wbdone;
  output imemdone;
  output [3:0] wbbyteen;
  output wben;

  supply1 vdd;
  supply0 gnd;
  wire imemdonemem;

  muddlib07__mux2_c_1x imemdonememmux(.d0(gnd), .d1(memdone), .s(ion), 
      .y(imemdonemem));
  muddlib07__mux2_c_1x imemdonemux(.d0(imemdonemem), .d1(wbdone), 
      .s(swc_imemrwbb), .y(imemdone));
  memsys_final__buftri_1x_4 wbbyteeni(.d(imembyteen[3:0]), .en(swc_imemrwbb), 
      .y(wbbyteen[3:0]));
  muddlib07__buftri_c_1x wbeni(.d(imemen), .en(swc_imemrwbb), .y(wben));
endmodule   /* memsys_final__greenblock */

module memsys_final__icache(adr, adr_1, byteen, en, memdone, ph1, ph2, reset, 
      rwb, done, membyteen, memen, data, memdata);
  input [27:0] adr;
  input [29:29] adr_1;
  input [3:0] byteen;
  input en;
  input memdone;
  input ph1;
  input ph2;
  input reset;
  input rwb;
  output done;
  output [3:0] membyteen;
  output memen;
  input [31:0] data;
  input [31:0] memdata;

  supply1 vdd;
  supply0 gnd;
  wire bypass, cacheramrwb, reading, valid, validnew, waiting_b;
  wire [31:0] cacheline;
  wire [31:0] cachelinenew;
  wire [19:0] tagdata;

  memsys_final__byteenlog byteenlo_0(.byteen(byteen[3:0]), .memdone(memdone), 
      .reading(reading), .validnew(validnew));
  memsys_final__cachecontroller cachecon_2(.adr(adr[27:7]), 
      .adr_1(adr_1[29:29]), .en(en), .memdone(memdone), .reset(reset), 
      .rwb(rwb), .tagdata(tagdata[19:0]), .valid(valid), .bypass(bypass), 
      .done(done), .reading(reading), .waiting(memen), .ph1(ph1), .ph2(ph2));
  memsys_final__cacheram cacheram_1(.adr(adr[6:0]), .din({cachelinenew[31], 
      cachelinenew[30], cachelinenew[29], cachelinenew[28], cachelinenew[27], 
      adr[26], cachelinenew[26], adr[25], cachelinenew[25], adr[24], 
      cachelinenew[24], adr[23], cachelinenew[23], adr[22], cachelinenew[22], 
      adr[21], cachelinenew[21], adr[20], cachelinenew[20], adr[19], 
      cachelinenew[19], adr[18], cachelinenew[18], adr[17], cachelinenew[17], 
      adr[16], cachelinenew[16], adr[15], cachelinenew[15], adr[14], 
      cachelinenew[14], adr[13], cachelinenew[13], adr[12], cachelinenew[12], 
      adr[11], cachelinenew[11], adr[10], cachelinenew[10], adr[9], 
      cachelinenew[9], adr[8], cachelinenew[8], adr[7], cachelinenew[7], 
      cachelinenew[6], cachelinenew[5], cachelinenew[4], cachelinenew[3], 
      cachelinenew[2], validnew, cachelinenew[1], cachelinenew[0]}), .ph1(ph1), 
      .ph2(ph2), .rwb(cacheramrwb), .dout({cacheline[31], cacheline[30], 
      cacheline[29], cacheline[28], cacheline[27], tagdata[19], cacheline[26], 
      tagdata[18], cacheline[25], tagdata[17], cacheline[24], tagdata[16], 
      cacheline[23], tagdata[15], cacheline[22], tagdata[14], cacheline[21], 
      tagdata[13], cacheline[20], tagdata[12], cacheline[19], tagdata[11], 
      cacheline[18], tagdata[10], cacheline[17], tagdata[9], cacheline[16], 
      tagdata[8], cacheline[15], tagdata[7], cacheline[14], tagdata[6], 
      cacheline[13], tagdata[5], cacheline[12], tagdata[4], cacheline[11], 
      tagdata[3], cacheline[10], tagdata[2], cacheline[9], tagdata[1], 
      cacheline[8], tagdata[0], cacheline[7], cacheline[6], cacheline[5], 
      cacheline[4], cacheline[3], cacheline[2], valid, cacheline[1], 
      cacheline[0]}));
  memsys_final__dataout dataout_1(.cacheline(cacheline[31:0]), .rwb(rwb), 
      .waiting(memen), .data(data[31:0]), .memdata(memdata[31:0]));
  muddlib07__inv_1x inv_1x_0(.a(memen), .y(waiting_b));
  memsys_final__mux2_1x_32 mux2_1x__2(.d0(data[31:0]), .d1(memdata[31:0]), 
      .s(reading), .y(cachelinenew[31:0]));
  memsys_final__mux2_1x_4 mux2_4_0(.d0(byteen[3:0]), .d1({vdd, vdd, vdd, vdd}), 
      .s(reading), .y(membyteen[3:0]));
  muddlib07__or2_1x or2_1x_0(.a(bypass), .b(waiting_b), .y(cacheramrwb));
endmodule   /* memsys_final__icache */

module muddlib07__nor2_1x(a, b, y);
  input a;
  input b;
  output y;

  supply1 vdd;
  supply0 gnd;
  wire net_9;

  tranif1 nmos_0(gnd, y, a);
  tranif1 nmos_1(gnd, y, b);
  tranif0 pmos_0(y, net_9, b);
  tranif0 pmos_1(net_9, vdd, a);
endmodule   /* muddlib07__nor2_1x */

module memsys_final__decoder_msc(a, y);
  input [1:0] a;
  output [3:0] y;

  supply1 vdd;
  supply0 gnd;
  wire a0, a0_b, a1, a1_b;

  muddlib07__invbuf_4x invbuf_4_0(.s(a[0]), .s_out(a0), .sb_out(a0_b));
  muddlib07__invbuf_4x invbuf_4_1(.s(a[1]), .s_out(a1), .sb_out(a1_b));
  muddlib07__nor2_1x nor2_1x_0(.a(a0_b), .b(a1), .y(y[1]));
  muddlib07__nor2_1x nor2_1x_1(.a(a0), .b(a1_b), .y(y[2]));
  muddlib07__nor2_1x nor2_1x_2(.a(a0_b), .b(a1_b), .y(y[3]));
  muddlib07__nor2_1x nor2_1x_3(.a(a0), .b(a1), .y(y[0]));
endmodule   /* memsys_final__decoder_msc */

module muddlib07__nand3_1x(a, b, c, y);
  input a;
  input b;
  input c;
  output y;

  supply1 vdd;
  supply0 gnd;
  wire net_15, net_4;

  tranif1 nmos_0(net_15, net_4, b);
  tranif1 nmos_1(net_4, y, a);
  tranif1 nmos_2(gnd, net_15, c);
  tranif0 pmos_0(y, vdd, a);
  tranif0 pmos_1(y, vdd, b);
  tranif0 pmos_2(y, vdd, c);
endmodule   /* muddlib07__nand3_1x */

module memsys_final__nextstatelog(dmemen, dmemrwb, imemen, imemrwb, memdone, 
      state, swc, wbmemen, nextstate);
  input dmemen;
  input dmemrwb;
  input imemen;
  input imemrwb;
  input memdone;
  input [1:0] state;
  input swc;
  input wbmemen;
  output [1:0] nextstate;

  supply1 vdd;
  supply0 gnd;
  wire S_READY, dmem, dmem_b, imem_b, memdone_b, net_10, net_101, net_169;
  wire net_244, net_255, net_257, net_47, net_72, net_8, net_91, wbmemen_b;

  muddlib07__and2_1x and2_1x_5(.a(net_10), .b(net_255), .y(net_8));
  muddlib07__inv_1x inv_1x_1(.a(wbmemen), .y(wbmemen_b));
  muddlib07__inv_1x inv_1x_2(.a(memdone), .y(memdone_b));
  muddlib07__inv_1x inv_1x_3(.a(imem_b), .y(net_10));
  muddlib07__inv_1x inv_1x_4(.a(dmem_b), .y(dmem));
  muddlib07__nand2_1x nand2_1x_5(.a(state[1]), .b(memdone_b), .y(net_91));
  muddlib07__nand2_1x nand2_1x_6(.a(imem_b), .b(dmem_b), .y(net_101));
  muddlib07__nand2_1x nand2_1x_7(.a(imemen), .b(imemrwb), .y(imem_b));
  muddlib07__nand2_1x nand2_1x_8(.a(dmemen), .b(dmemrwb), .y(dmem_b));
  muddlib07__nand2_1x nand2_1x_9(.a(S_READY), .b(net_244), .y(net_47));
  muddlib07__nand2_1x nand2_1x_11(.a(memdone_b), .b(state[0]), .y(net_169));
  muddlib07__nand2_1x nand2_1x_12(.a(net_72), .b(net_91), .y(nextstate[1]));
  muddlib07__nand2_1x nand2_1x_13(.a(net_169), .b(net_47), .y(nextstate[0]));
  muddlib07__nand3_1x nand3_1x_0(.a(net_101), .b(wbmemen_b), .c(S_READY), 
      .y(net_72));
  muddlib07__nor2_1x nor2_1x_0(.a(state[0]), .b(state[1]), .y(S_READY));
  muddlib07__nor2_1x nor2_1x_1(.a(swc), .b(dmem), .y(net_257));
  muddlib07__or2_1x or2_1x_3(.a(wbmemen), .b(net_8), .y(net_244));
  muddlib07__or2_1x or2_1x_5(.a(swc), .b(net_257), .y(net_255));
endmodule   /* memsys_final__nextstatelog */

module memsys_final__memsyscontroller(dmemen, dmemrwb, imemen, imemrwb, 
      memdone, reset, swc, wbmemen, don, ion, memen, state, wbon, ph1, ph2);
  input dmemen;
  input dmemrwb;
  input imemen;
  input imemrwb;
  input memdone;
  input reset;
  input swc;
  input wbmemen;
  output don;
  output ion;
  output memen;
  output [1:0] state;
  output wbon;
  input ph1;
  input ph2;

  supply1 vdd;
  supply0 gnd;
  wire ornextstate, reset_b;
  wire [1:0] nextstate;
  wire [3:0] onnext;

  memsys_final__decoder_msc decoder_0(.a(nextstate[1:0]), .y(onnext[3:0]));
  muddlib07__flopr_c_1x flopr_c__0(.d(nextstate[0]), .resetb(reset_b), 
      .q(state[0]), .ph1(ph1), .ph2(ph2));
  muddlib07__flopr_c_1x flopr_c__1(.d(nextstate[1]), .resetb(reset_b), 
      .q(state[1]), .ph1(ph1), .ph2(ph2));
  muddlib07__flopr_c_1x flopr_c__2(.d(ornextstate), .resetb(reset_b), 
      .q(memen), .ph1(ph1), .ph2(ph2));
  muddlib07__flopr_c_1x flopr_c__3(.d(onnext[3]), .resetb(reset_b), .q(ion), 
      .ph1(ph1), .ph2(ph2));
  muddlib07__flopr_c_1x flopr_c__4(.d(onnext[2]), .resetb(reset_b), .q(don), 
      .ph1(ph1), .ph2(ph2));
  muddlib07__flopr_c_1x flopr_c__5(.d(onnext[1]), .resetb(reset_b), .q(wbon), 
      .ph1(ph1), .ph2(ph2));
  muddlib07__inv_1x inv_1x_5(.a(reset), .y(reset_b));
  memsys_final__nextstatelog nextstat_0(.dmemen(dmemen), .dmemrwb(dmemrwb), 
      .imemen(imemen), .imemrwb(imemrwb), .memdone(memdone), 
      .state(state[1:0]), .swc(swc), .wbmemen(wbmemen), 
      .nextstate(nextstate[1:0]));
  muddlib07__or2_1x or2_1x_1(.a(nextstate[0]), .b(nextstate[1]), 
      .y(ornextstate));
endmodule   /* memsys_final__memsyscontroller */

module muddlib07__mux4_c_1x(d0, d1, d2, d3, s0, s1, y);
  input d0;
  input d1;
  input d2;
  input d3;
  input s0;
  input s1;
  output y;

  supply1 vdd;
  supply0 gnd;
  wire net_28, net_29, net_30, net_5, net_50, net_51, net_56, net_57, net_58;
  wire net_6, net_68, net_70, net_8, s0b, s1b;

  tranif1 nmos_0(gnd, net_5, d0);
  tranif1 nmos_1(gnd, net_6, d1);
  tranif1 nmos_3(net_5, net_8, s0b);
  tranif1 nmos_4(net_6, net_8, s0);
  tranif1 nmos_5(net_8, net_50, s1b);
  tranif1 nmos_7(gnd, net_70, d3);
  tranif1 nmos_8(net_68, net_51, s0b);
  tranif1 nmos_9(net_70, net_51, s0);
  tranif1 nmos_10(net_51, net_50, s1);
  tranif1 nmos_11(gnd, net_68, d2);
  tranif1 nmos_12(gnd, y, net_50);
  tranif1 nmos_13(gnd, s1b, s1);
  tranif1 nmos_14(gnd, s0b, s0);
  tranif0 pmos_0(net_50, net_30, s1);
  tranif0 pmos_2(net_30, net_28, s0);
  tranif0 pmos_3(net_28, vdd, d0);
  tranif0 pmos_4(net_30, net_29, s0b);
  tranif0 pmos_5(net_29, vdd, d1);
  tranif0 pmos_7(net_58, net_56, s0);
  tranif0 pmos_8(net_56, vdd, d2);
  tranif0 pmos_9(net_58, net_57, s0b);
  tranif0 pmos_10(net_57, vdd, d3);
  tranif0 pmos_11(net_50, net_58, s1b);
  tranif0 pmos_12(y, vdd, net_50);
  tranif0 pmos_13(s1b, vdd, s1);
  tranif0 pmos_14(s0b, vdd, s0);
endmodule   /* muddlib07__mux4_c_1x */

module memsys_final__orangeblock(memdone, state, wbon, memrwb, wbmemdone);
  input memdone;
  input [1:0] state;
  input wbon;
  output memrwb;
  output wbmemdone;

  supply1 vdd;
  supply0 gnd;
  muddlib07__mux4_c_1x memrwbmux(.d0(vdd), .d1(gnd), .d2(vdd), .d3(vdd), 
      .s0(state[0]), .s1(state[1]), .y(memrwb));
  muddlib07__mux2_c_1x wbmemdonemux(.d0(gnd), .d1(memdone), .s(wbon), 
      .y(wbmemdone));
endmodule   /* memsys_final__orangeblock */

module muddlib07__a22o2_1x(a, b, c, d, y);
  input a;
  input b;
  input c;
  input d;
  output y;

  supply1 vdd;
  supply0 gnd;
  wire net_3, net_5, net_7, net_8;

  tranif1 nmos_0(gnd, net_8, a);
  tranif1 nmos_1(gnd, net_7, c);
  tranif1 nmos_2(net_8, net_5, b);
  tranif1 nmos_3(net_7, net_5, d);
  tranif1 nmos_4(gnd, y, net_5);
  tranif0 pmos_0(net_5, net_3, c);
  tranif0 pmos_1(net_3, vdd, a);
  tranif0 pmos_2(net_5, net_3, d);
  tranif0 pmos_3(net_3, vdd, b);
  tranif0 pmos_4(y, vdd, net_5);
endmodule   /* muddlib07__a22o2_1x */

module memsys_final__mux4_1x_4(d0, d1, d2, d3, s, y);
  input [3:0] d0;
  input [3:0] d1;
  input [3:0] d2;
  input [3:0] d3;
  input [1:0] s;
  output [3:0] y;

  supply1 vdd;
  supply0 gnd;
  wire net_37, net_38, net_39, net_40;

  muddlib07__mux4_dp_1x mux4_3_(.d0(d0[3]), .d1(d1[3]), .d2(d2[3]), .d3(d3[3]), 
      .s0(net_37), .s0b(net_38), .s1(net_39), .s1b(net_40), .y(y[3]));
  muddlib07__mux4_dp_1x mux4_2_(.d0(d0[2]), .d1(d1[2]), .d2(d2[2]), .d3(d3[2]), 
      .s0(net_37), .s0b(net_38), .s1(net_39), .s1b(net_40), .y(y[2]));
  muddlib07__mux4_dp_1x mux4_1_(.d0(d0[1]), .d1(d1[1]), .d2(d2[1]), .d3(d3[1]), 
      .s0(net_37), .s0b(net_38), .s1(net_39), .s1b(net_40), .y(y[1]));
  muddlib07__mux4_dp_1x mux4_0_(.d0(d0[0]), .d1(d1[0]), .d2(d2[0]), .d3(d3[0]), 
      .s0(net_37), .s0b(net_38), .s1(net_39), .s1b(net_40), .y(y[0]));
  memsys_final__mux4_zip mux4_zip_0(.s(s[1:0]), .s0_out(net_37), 
      .s0b_out(net_38), .s1_out(net_39), .s1b_out(net_40));
endmodule   /* memsys_final__mux4_1x_4 */

module memsys_final__redblock(dmembyteen, dmemrwb, imembyteen, imemrwb, state, 
      swc, wbmembyteen, membyteen, wben);
  input [3:0] dmembyteen;
  input dmemrwb;
  input [3:0] imembyteen;
  input imemrwb;
  input [1:0] state;
  input swc;
  input [3:0] wbmembyteen;
  output [3:0] membyteen;
  output wben;

  supply1 vdd;
  supply0 gnd;
  wire swcb, wbenz_en;

  muddlib07__a22o2_1x a22o2_1x_0(.a(swc), .b(imemrwb), .c(swcb), .d(dmemrwb), 
      .y(wbenz_en));
  muddlib07__inv_1x inv_1x_0(.a(swc), .y(swcb));
  memsys_final__mux4_1x_4 membyteenmux(.d0({gnd, gnd, gnd, vdd}), 
      .d1(wbmembyteen[3:0]), .d2(dmembyteen[3:0]), .d3(imembyteen[3:0]), 
      .s(state[1:0]), .y(membyteen[3:0]));
  muddlib07__buftri_c_1x wbenz(.d(gnd), .en(wbenz_en), .y(wben));
endmodule   /* memsys_final__redblock */

module memsys_final__wb_tribuf_en(dmemrwb, imemrwb, swc, swc_imemrwbb, 
      swcb_dmemrwbb);
  input dmemrwb;
  input imemrwb;
  input swc;
  output swc_imemrwbb;
  output swcb_dmemrwbb;

  supply1 vdd;
  supply0 gnd;
  wire imemrwbb;

  muddlib07__and2_1x and2_1x_0(.a(swc), .b(imemrwbb), .y(swc_imemrwbb));
  muddlib07__inv_1x inv_1x_0(.a(imemrwb), .y(imemrwbb));
  muddlib07__nor2_1x nor2_1x_0(.a(swc), .b(dmemrwb), .y(swcb_dmemrwbb));
endmodule   /* memsys_final__wb_tribuf_en */

module memsys_final__12TSRAM(bit, read, read_b, write, write_b, bit_read);
  input bit;
  input read;
  input read_b;
  input write;
  input write_b;
  output bit_read;

  supply1 vdd;
  supply0 gnd;
  wire net_56, net_58, net_59, net_6, net_61;
  trireg net_5;

  tranif1 nmos_1(net_58, net_5, net_6);
  tranif1 nmos_2(gnd, net_58, write_b);
  tranif1 nmos_3(gnd, net_6, net_5);
  tranif1 nmos_4(net_61, bit_read, read);
  tranif1 nmos_5(gnd, net_61, net_6);
  tranif1 nmos_6(bit, net_5, write);
  tranif0 pmos_0(net_5, bit, write_b);
  tranif0 pmos_1(net_56, vdd, write);
  tranif0 pmos_2(net_5, net_56, net_6);
  tranif0 pmos_3(net_6, vdd, net_5);
  tranif0 pmos_4(net_59, vdd, net_6);
  tranif0 pmos_5(bit_read, net_59, read_b);
endmodule   /* memsys_final__12TSRAM */

module muddlib07__inv_6x(a, y);
  input a;
  output y;

  supply1 vdd;
  supply0 gnd;
  tranif1 nmos_0(gnd, y, a);
  tranif1 nmos_1(gnd, y, a);
  tranif0 pmos_0(y, vdd, a);
  tranif0 pmos_1(y, vdd, a);
endmodule   /* muddlib07__inv_6x */

module memsys_final__endec(S0, S1, en, d, d_1, d_2, d_3);
  input S0;
  input S1;
  input en;
  output [0:0] d;
  output [1:1] d_1;
  output [2:2] d_2;
  output [3:3] d_3;

  supply1 vdd;
  supply0 gnd;
  wire net_127, net_129;

  muddlib07__and3_1x and3_1x_0(.a(net_127), .b(net_129), .c(en), .y(d[0]));
  muddlib07__and3_1x and3_1x_1(.a(S0), .b(net_129), .c(en), .y(d_1[1]));
  muddlib07__and3_1x and3_1x_2(.a(net_127), .b(S1), .c(en), .y(d_2[2]));
  muddlib07__and3_1x and3_1x_3(.a(S1), .b(S0), .c(en), .y(d_3[3]));
  muddlib07__inv_1x inv_4x_0(.a(S1), .y(net_129));
  muddlib07__inv_1x inv_4x_1(.a(S0), .y(net_127));
endmodule   /* memsys_final__endec */

module memsys_final__SRAMarray(clk, ptr, rwb, writeptr, WBOUT, data);
  input clk;
  input [1:0] ptr;
  input rwb;
  input [1:0] writeptr;
  output [62:0] WBOUT;
  output [62:0] data;

  supply1 vdd;
  supply0 gnd;
  wire net_120, net_135, net_136, net_143, net_144, net_145, net_151, net_153;
  wire net_159, net_16, net_161, net_169, net_170, net_177, net_178, net_187;
  wire net_188, net_195, net_196, net_20, net_24, net_59, net_83, net_88;
  wire net_92, net_94;

  memsys_final__12TSRAM a_62_(.bit(data[62]), .read(net_135), .read_b(net_136), 
      .write(net_143), .write_b(net_144), .bit_read(WBOUT[62]));
  memsys_final__12TSRAM a_61_(.bit(data[61]), .read(net_135), .read_b(net_136), 
      .write(net_143), .write_b(net_144), .bit_read(WBOUT[61]));
  memsys_final__12TSRAM a_60_(.bit(data[60]), .read(net_135), .read_b(net_136), 
      .write(net_143), .write_b(net_144), .bit_read(WBOUT[60]));
  memsys_final__12TSRAM a_59_(.bit(data[59]), .read(net_135), .read_b(net_136), 
      .write(net_143), .write_b(net_144), .bit_read(WBOUT[59]));
  memsys_final__12TSRAM a_58_(.bit(data[58]), .read(net_135), .read_b(net_136), 
      .write(net_143), .write_b(net_144), .bit_read(WBOUT[58]));
  memsys_final__12TSRAM a_57_(.bit(data[57]), .read(net_135), .read_b(net_136), 
      .write(net_143), .write_b(net_144), .bit_read(WBOUT[57]));
  memsys_final__12TSRAM a_56_(.bit(data[56]), .read(net_135), .read_b(net_136), 
      .write(net_143), .write_b(net_144), .bit_read(WBOUT[56]));
  memsys_final__12TSRAM a_55_(.bit(data[55]), .read(net_135), .read_b(net_136), 
      .write(net_143), .write_b(net_144), .bit_read(WBOUT[55]));
  memsys_final__12TSRAM a_54_(.bit(data[54]), .read(net_135), .read_b(net_136), 
      .write(net_143), .write_b(net_144), .bit_read(WBOUT[54]));
  memsys_final__12TSRAM a_53_(.bit(data[53]), .read(net_135), .read_b(net_136), 
      .write(net_143), .write_b(net_144), .bit_read(WBOUT[53]));
  memsys_final__12TSRAM a_52_(.bit(data[52]), .read(net_135), .read_b(net_136), 
      .write(net_143), .write_b(net_144), .bit_read(WBOUT[52]));
  memsys_final__12TSRAM a_51_(.bit(data[51]), .read(net_135), .read_b(net_136), 
      .write(net_143), .write_b(net_144), .bit_read(WBOUT[51]));
  memsys_final__12TSRAM a_50_(.bit(data[50]), .read(net_135), .read_b(net_136), 
      .write(net_143), .write_b(net_144), .bit_read(WBOUT[50]));
  memsys_final__12TSRAM a_49_(.bit(data[49]), .read(net_135), .read_b(net_136), 
      .write(net_143), .write_b(net_144), .bit_read(WBOUT[49]));
  memsys_final__12TSRAM a_48_(.bit(data[48]), .read(net_135), .read_b(net_136), 
      .write(net_143), .write_b(net_144), .bit_read(WBOUT[48]));
  memsys_final__12TSRAM a_47_(.bit(data[47]), .read(net_135), .read_b(net_136), 
      .write(net_143), .write_b(net_144), .bit_read(WBOUT[47]));
  memsys_final__12TSRAM a_46_(.bit(data[46]), .read(net_135), .read_b(net_136), 
      .write(net_143), .write_b(net_144), .bit_read(WBOUT[46]));
  memsys_final__12TSRAM a_45_(.bit(data[45]), .read(net_135), .read_b(net_136), 
      .write(net_143), .write_b(net_144), .bit_read(WBOUT[45]));
  memsys_final__12TSRAM a_44_(.bit(data[44]), .read(net_135), .read_b(net_136), 
      .write(net_143), .write_b(net_144), .bit_read(WBOUT[44]));
  memsys_final__12TSRAM a_43_(.bit(data[43]), .read(net_135), .read_b(net_136), 
      .write(net_143), .write_b(net_144), .bit_read(WBOUT[43]));
  memsys_final__12TSRAM a_42_(.bit(data[42]), .read(net_135), .read_b(net_136), 
      .write(net_143), .write_b(net_144), .bit_read(WBOUT[42]));
  memsys_final__12TSRAM a_41_(.bit(data[41]), .read(net_135), .read_b(net_136), 
      .write(net_143), .write_b(net_144), .bit_read(WBOUT[41]));
  memsys_final__12TSRAM a_40_(.bit(data[40]), .read(net_135), .read_b(net_136), 
      .write(net_143), .write_b(net_144), .bit_read(WBOUT[40]));
  memsys_final__12TSRAM a_39_(.bit(data[39]), .read(net_135), .read_b(net_136), 
      .write(net_143), .write_b(net_144), .bit_read(WBOUT[39]));
  memsys_final__12TSRAM a_38_(.bit(data[38]), .read(net_135), .read_b(net_136), 
      .write(net_143), .write_b(net_144), .bit_read(WBOUT[38]));
  memsys_final__12TSRAM a_37_(.bit(data[37]), .read(net_135), .read_b(net_136), 
      .write(net_143), .write_b(net_144), .bit_read(WBOUT[37]));
  memsys_final__12TSRAM a_36_(.bit(data[36]), .read(net_135), .read_b(net_136), 
      .write(net_143), .write_b(net_144), .bit_read(WBOUT[36]));
  memsys_final__12TSRAM a_35_(.bit(data[35]), .read(net_135), .read_b(net_136), 
      .write(net_143), .write_b(net_144), .bit_read(WBOUT[35]));
  memsys_final__12TSRAM a_34_(.bit(data[34]), .read(net_135), .read_b(net_136), 
      .write(net_143), .write_b(net_144), .bit_read(WBOUT[34]));
  memsys_final__12TSRAM a_33_(.bit(data[33]), .read(net_135), .read_b(net_136), 
      .write(net_143), .write_b(net_144), .bit_read(WBOUT[33]));
  memsys_final__12TSRAM a_32_(.bit(data[32]), .read(net_135), .read_b(net_136), 
      .write(net_143), .write_b(net_144), .bit_read(WBOUT[32]));
  memsys_final__12TSRAM a_31_(.bit(data[31]), .read(net_135), .read_b(net_136), 
      .write(net_143), .write_b(net_144), .bit_read(WBOUT[31]));
  memsys_final__12TSRAM a_30_(.bit(data[30]), .read(net_135), .read_b(net_136), 
      .write(net_143), .write_b(net_144), .bit_read(WBOUT[30]));
  memsys_final__12TSRAM a_29_(.bit(data[29]), .read(net_135), .read_b(net_136), 
      .write(net_143), .write_b(net_144), .bit_read(WBOUT[29]));
  memsys_final__12TSRAM a_28_(.bit(data[28]), .read(net_135), .read_b(net_136), 
      .write(net_143), .write_b(net_144), .bit_read(WBOUT[28]));
  memsys_final__12TSRAM a_27_(.bit(data[27]), .read(net_135), .read_b(net_136), 
      .write(net_143), .write_b(net_144), .bit_read(WBOUT[27]));